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52
$000
$003
PMRA $004
SMR $005
SRL $006
SRU $007
TMA $008
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
ACR $016
ADRL $017
ADRU $018
AMR1 $019
AMR2 $01A
$020
$023
PMRB $024
PMRC $025
TMB2 $026
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
DCR8 $038
$03F
D3/BUZZ
R00/SCK
R33/AN3
D4/STOPC
R03/TOC
R32/AN2
R01/SI
R02/SO
R31/AN1
R4/AN4 to AN7
R30/AN0
D2/EVNB
D1/INT1
D0/INT0
: Unused
Note: * Applies to the HD404358/HD404358R Series. Unused in the HD404318 Series.
RAM address
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt control bit area
Transfer clock selection
Serial data register (lower)
Serial data register (upper)
Clock source setting (timer A)
Clock source setting (timer B)
Auto-reload on/off
Timer B register (lower)
Timer B register (upper)
Pull-up MOS control
Reload on/off
SO PMOS control
Clock source setting (timer C)
Timer C register (lower)
Timer C register (upper)
A/D execution channel selection (AN0 to AN7)
A/D data register (lower)
A/D data register (upper)
Register flag area
Alarm frequency
Input capture setting
SO idle H/L setting
Transfer clock selection
EVNB edge selection
Port D3 DCR*
Port D7 DCR*
Port D2 DCR*
Port D6 DCR*
Port D1 DCR*
Port D5 DCR*
Port D0 DCR*
Port D4 DCR*
Port D8 DCR*
Port R03 DCR
Port R13 DCR*
Port R23 DCR*
Port R33 DCR
Port R43 DCR
Port R02 DCR
Port R12 DCR*
Port R22 DCR*
Port R32 DCR
Port R42 DCR
Port R01 DCR
Port R11 DCR*
Port R21 DCR*
Port R31 DCR
Port R41 DCR
Port R00 DCR
Port R10 DCR*
Port R20 DCR*
Port R30 DCR
Port R40 DCR
Port R83 DCR*
Port R82 DCR*
Port R81 DCR*
Port R80 DCR*
A/D conversion time
Figure 2-11 HD404318, HD404358 and HD404358R Series
Special Register Area Structure