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6.5
Watch Mode
6.5.1
Entering Watch Mode
The system switches to watch mode from active when a STOP instruction is executed when the
TMA3 bit in TMA is cleared to 1. The system also switches to watch mode from subactive mode
when either a STOP or SBY instruction is executed either with LSON set to 1 or with DTON
cleared to 0.
In watch mode the system clock stops but the subsystem clock continues to operate, and timer A
operates (in clock time base mode) from the subsystem clock. All other built-in peripheral
modules stop. RAM and the D and R ports set to output retain their values prior to entering watch
mode. Power consumption in watch mode is the second lowest, exceeding only that in stop mode.
Watch mode is convenient when only clock operation is required.
6.5.2
Clearing Watch Mode
Watch mode can be cleared either by a
RESET pin input or an INT
0 or timer A interrupt.
(1) Clearing with a
RESET Pin Input: When the RESET pin goes low the system enters the
reset state and watch mode is cleared.
(2) Clearing with an
INT
0 or Timer A Interrupt: Watch mode is cleared when an INT0 or timer
A interrupt occurs and the corresponding IF is 1 and IM is 0. If LSON was 0 at that time the
system switches to active mode, and if LSON was 1, the system switches to subactive mode.
After the transition the instruction following the STOP or SBY instruction is executed. If the
interrupt enable flag (IE) is 1, the corresponding interrupt handler will be executed. If IE is 0, the
interrupt is deferred and the execution of the immediately preceding instruction sequence
continues. (See figure 6-3.)