
452
Use the following procedure for data transmission in external clock mode.
1. Setup transmission mode by setting the PMRA1 and PMRA0 bits to 01.
2. Setup external clock mode by setting the SMR3 to SMR0 bits to 1111.
The serial interface internal states are initialized when SMR is written.
3
Select either a low or high level SO pin idle output by setting the PMRC1 bit. The SO pin will
immediately go to either the high or low level when PMRC1 is written.
4
Write the data to be transmitted to the SRL/U pair.
5
Execute an STS instruction. The serial interface will switch from the STS instruction wait state
to the transfer clock wait state.
When the external clock is applied, the serial interface will switch from the transfer clock wait
state to the transfer state on the first transfer clock falling edge, and the serial interface will
begin the transmission operation.
6. When eight transfer clock cycles have been input, OC is cleared to 000 and IFS is set to 1. At
the same time the serial interface switches from the transfer state to the transfer clock wait
state thus completing the transmission operation.
After the transfer completes, the SO pin holds the value of the MSB of the transmitted data. The
output value on the SO pin can be changed by setting the PMRC1 bit.
In the transfer clock wait state, if the transfer clock continues to be input, data transmission
operations are repeated. Also, the serial interface can be returned to the STS instruction wait state
to prepare for the next transmission by performing a dummy write to the SMR register.
If the SMR register is written during a transmission operation, OC is cleared to 0 and IFS is set to
1. At the same time the serial interface switches to the STS instruction wait state and the
transmission is aborted.
Figure 20-6 shows the operation sequence for data transmission in external clock mode.