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14.2.2
System Clock Selection Register 2 (SSR2: $028)
SSR2 is a 2-bit write-only register that selects the system clock divisor.
SSR2 is initialized to $0 on reset and in stop mode.
Bit
Initial value
Read/Write
3
—
0
SSR20
0
W
2
—
1
SSR21
0
W
0
1
System clock divisor selection
0
1
0
1
Unused
Division by 4 (fcyc = fOSC/4)
Division by 8 (fcyc = fOSC/8)
Division by 16 (fcyc = fOSC/16)
Division by 32 (fcyc = fOSC/32)
Bits 1 and 0—System Clock Selection (SSR21, SSR20): These bits set the system clock divisor
to be 4, 8, 16, or 32, i.e., the system oscillator frequency is divided by 4, 8, 16, or 32. (f
cyc = fOSC/4,
f
OSC/8, fOSC/16, or fOSC/32) This setting only takes effect when watch mode is entered. That is, the
system clock must be stopped to change the divisor.
SSR21
SSR20
Description
0
The system clock divisor is 4 (f
cyc = fOSC/4)
(initial value)
1
The system clock divisor is 8 (f
cyc = fOSC/8)
1
0
The system clock divisor is 16 (f
cyc = fOSC/16)
1
The system clock divisor is 32 (f
cyc = fOSC/32)
There are two methods for changing the system clock divisor as follows.
1. In active mode, set the divisor by writing the SSR21 and SSR20 bits. At this point the
immediately prior divisor setting remains in effect. Now, switch to watch mode and then return
to active mode. When the system returns to active mode the new clock divisor will be in effect.
2. In subactive mode, set the divisor by writing the SSR21 and SSR20 bits. Then, return to active
mode by passing through watch mode. When the system returns to active mode the new clock
divisor will be in effect. (The change will also take effect for direct transition to active mode.)