
298
12.1.2
I/O Control
R1 and R2 are medium voltage NMOS open drain I/O ports and the D, R0, and R3 to R9 ports are
standard voltage I/O ports. The different port types have different circuit structures as follows.
(1) Medium Voltage NMOS Open Drain I/O Pin Circuit: R1 and R2 are medium voltage
NMOS open drain I/O ports and I/O through these ports is controlled by the port data registers
(PDR) and the data control registers (DCR). When the DCR bit corresponding to a given pin is 1,
that pin functions as an output pin and when the value in the PDR is 0, the pin’s NMOS transistor
turns on and the pin outputs a low level voltage. When the value in the PDR is 1 the pin goes to
the high impedance state. When a given DCR bit is 0, the corresponding pin functions as an input
pin.
(2) Standard Voltage CMOS Three State I/O Pin Circuit: The pins in the D, R0, and R3 to R9
ports are standard voltage CMOS three state I/O ports. I/O through these ports is controlled by the
PDRs and the data control registers (DCD or DCR). When the DCD or DCR bit corresponding to
a given pin is 1, that pin functions as an output pin and outputs the value in the PDR. When a
given DCD or DCR bit is 0, the corresponding pin functions as an input pin.
(3) Pull-Up MOS Control: Each I/O pin in the D, R0 and R3 to R9 ports has a built-in
programmable pull-up MOS transistor. When the miscellaneous register (MIS) MIS3 bit is set to 1
the pull-up MOS transistor for pins for which the corresponding PDR is set to 1 will be turned on.
Thus the on/off state of each pin can be controlled independently by the PDRs. Note that the pull-
up MOS transistor on/off settings are independent of the pin settings for use as built-in peripheral
module pins.
Table 12-2 shows how register settings control the port I/O pins.
Table 12-2 Register Settings for I/O Pin Control
MIS3
0
1
DCD, DCR
0101
PDR
01010101
CMOS buffer
PMOS
—
On
—
On
NMOS
On
—
On
—
Pull-up MOS transistor
—
On
—
On
Notes: 1. —: Off
2. The PDR registers are not allocated addresses in RAM. The PDR registers are
accessed by special-purpose I/O instructions.