
471
20.4
Interrupts
The serial interface interrupt source is generated when the serial interface switches from the
transfer state to any other state, i.e., when OC is cleared to 000. IFS is set to 1 when the serial
interface interrupt source occurs.
IFS is never cleared automatically, even if the interrupt is accepted. The interrupt handling routine
should clear IFS to 0.
The serial interrupt can be independently enabled or masked with the serial interrupt mask (IMS)
in the interrupt control bit area.
20.5
Usage Notes
Keep the following points in mind when using the serial interface.
If PMRA is to be written in either the transfer clock wait state or the transfer state, the serial
interface should be re-initialized by writing to the SMR register.
In the transfer state, IFS is not set to 1 by writing to SMR or switching to another state by
executing an STS instruction during the first low level period of the transfer clock. To set the
IFS flag reliably, execute an input instruction for the R0
0 pin, which will be assigned to be the
SCK pin, and confirm that the SCK pin is at the high level. After this has been done, program
software to write to SMR or to execute the STS instruction.
Changes to the SMR register become valid two instruction cycles after the execution of the
instruction that wrote the register. Therefore application programs must be written so that the
STS instruction is executed only after a period of at least 2t
cyc has elapsed after the SMR
register was written.
MIS register control of the PMOS transistor on/off state is valid regardless of the PMRA
register R0
2/SO pin function selection.