
580
Table 25-32 AC Characteristics (HD404339 Series) (cont)
V
CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20 to 75°C unless specified
otherwise.
Applicable
Rated Value
Test
Item
Symbol Pins
Min
Typ
Max
Unit
Conditions
Notes
INT
0, INT1, and
EVNB high level
width
t
IH
INT
0, INT1,
EVNB
2
——
t
cyc /
t
subcyc
4
INT
0, INT1, and
EVNB low level
width
t
IL
INT
0, INT1,
EVNB
2
——
t
cyc /
t
subcyc
4
RESET low level
width
t
RSTL
RESET
2
——
t
cyc
5
STOPC low level
width
t
STPL
STOPC
1
——
t
RC
6
RESET rise time
t
RSTr
RESET
——
20
ms
5
STOPC rise time
t
STPr
STOPC
——
20
ms
6
Input capacitance
C
in
All input
pins other
than TEST
——
30
pF
f = 1 Mhz,
V
in = 0 V
TEST
——
30
f = 1 MHz,
7
——
180
V
in = 0 V
8
Notes: 1. When a sub-system oscillator (a 32.768 kHz crystal oscillator) is used, f
OSC must either
be in the range 0.4 MHz
≤ f
OSC ≤ 1.0 MHz or be in the range 1.6 MHz ≤ fOSC ≤ 4.5 MHz.
Furthermore, the SSR11 bit in the system clock selection register 1 (SSR1: $027) must
be set to indicate which of those ranges f
OSC falls in.
2. There are three cases where the oscillator stabilization period applies:
When power is first applied, the time between the point when V
CC reaches 4.0 V and
the point the oscillator is stable.
When stop mode is cleared, the time between the point when the
RESET input
reaches the low level and the point the oscillator is stable.
When stop mode is cleared, the time between the point when the
STOPC input
reaches the low level and the point the oscillator is stable.
To assure the time necessary to achieve stable oscillation at power on and when
clearing stop mode, apply a low level to the
RESET or STOPC input for at least t
RC.
Since the oscillator stabilization period varies with the details of the mounted circuit,
stray capacitances, and other factors, this value should be determined based on
thorough consultations with the manufacturer of the ceramic oscillator used.
3. See figure 25-25.
4. See figure 25-26.
5. See figure 25-27.
6. See figure 25-28.