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9.1.2
I/O Control
The D, R1, R2, and R8 ports are high voltage I/O ports, RA
1 is a 1-bit high voltage input port, and
R0, R3, and R4 are standard voltage I/O ports. The different port types have different circuit
structures as follows.
(1) High Voltage I/O Pin Circuit: The D, R1, R2, and R8 port pins are high voltage I/O pins that
have no I/O switching function. When a port data register is set to 1, the PMOS transistor turns on
and a high level voltage is output from the pin. When the PDR is set to 0, the pin goes to the open
state. If the built-in pull-down resistor mask option was selected, the V
disp voltage is output. When
external signals are applied, applications must set the PDR value to 0 so that the external (input)
and internal (output) signals do not collide at the pin.
Note that there are no pull-down resistors on the high voltage I/O pins in the ZTAT versions of
these microcomputers.
(2) Standard Voltage CMOS Three State I/O Pin Circuit: The pins in the R0, R3, and R4
ports are standard voltage CMOS three state I/O ports. I/O through these ports is controlled by the
PDRs and the data control registers (DCR). When the DCR bit corresponding to a given pin is 1,
that pin functions as an output pin and outputs the value in the PDR. When a given DCR bit is 0,
the corresponding pin functions as an input pin.
(3) Pull-Up MOS Control: Each I/O pin in the R0, R3, and R4 ports has a built-in programmable
pull-up MOS transistor. When the miscellaneous register (MIS) MIS3 bit is set to 1 the pull-up
MOS transistor for pins for which the corresponding PDR is set to 1 will be turned on. Thus the
on/off state of each pin can be controlled independently by the PDRs. Note that the pull-up MOS
transistor on/off settings are independent of the pin settings for use as built-in peripheral module
pins.
Table 9-2 shows how register settings control the port I/O pins.
Table 9-2
Register Settings for I/O Pin Control
MIS3
0
1
DCR
0101
PDR
01010101
CMOS buffer
PMOS
—
On
—
On
NMOS
On
—
On
—
Pull-up MOS transistor
—
On
—
On
Notes: 1. —: Off
2. The PDR registers are not allocated addresses in RAM. The PDR registers are
accessed by special-purpose I/O instructions.