參數(shù)資料
型號(hào)： HB52E89EM
廠商： Hitachi,Ltd.
英文描述： 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
中文描述： 64 MB的無(wú)緩沖SDRAM的內(nèi)存（64MB的未緩沖同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 36/64頁(yè)
文件大?。?/td> 2741K
代理商： HB52E89EM
HB52E88EM-F, HB52E89EM-F, HB52E168EN-F, HB52E169EN-F
36
Burst Sequence
Operation of the SDRAM module
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according
to the status of the bank select address (BA) pin, and the row address (AX0 to AX11) is activated by the A0
to A11 pins at the bank active command cycle. An interval of t
RCD
is required between the bank active com-
mand input and the following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the
column address and the bank select address (BA) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The CE latency and burst length must be specified at the mode register.
A2
A1
A0
Addressing(decimal)
Sequential
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0, 1, 2, 3, 4, 5, 6,
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
Interleave
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6, 5, 4, 3, 2, 1, 0,
1
1
0
Starting Ad.
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
Burst length = 8
A1
A0
Addressing(decimal)
Sequential
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0
0
1
1
0
1
0
1
Interleave
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Starting Ad.
Burst length = 4
A0
Addressing(decimal)
Sequential
0, 1,
1, 0,
0
1
Interleave
0, 1,
1, 0,
Starting Ad.
Burst length = 2
相關(guān)PDF資料
PDF描述
HB52E169E12 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM)
HB52E648EN 512 MB Unbuffered SDRAM DIMM(512 MB 未緩沖同步DRAM DIMM)
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HB52E649E12-A6B 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM
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