參數(shù)資料
型號(hào)： GCIXF1002ED
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 45/128頁
文件大小： 1262K
代理商： GCIXF1002ED
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
45
3.2.5
GMII Management Register Set
The following sections describe the individual GMII management register set as defined in the
IEEE 802.3z standard.
Any bit in these registers that has a fixed value is not writable.
Note:
These registers are accessible only in GPCS mode.
3.2.5.1
GMII Control Register
Mnemonic: GMII_CTL
Address: 50H
–
51H
The control register provides the mechanism to enable or disable Auto-Negotiation, restart
Auto-Negotiation, and allow for manual configuration when Auto-Negotiation is disabled.
Bit Name
Bit #
Bit Description
RST
15
Reset.
When set, causes reset to the GPCS logic and to the GMII management registers. When
reset, indicates normal operation. This bit is self clearing. The value of this bit remains at 1,
until the reset process is completed.
LPBK
14
External loopback.
When set, enables external loopback mode, and causes assertion of ewrap_{i} signal.
When reset, disables external loopback mode, and causes deassertion of ewrap_{i} signal.
SPEED_2
13
Speed selection.
This bit is fixed at the value of 0 and the value of bit 6 is fixed to 1, determining a speed
selection of 1000 Mb/s.
ANENBL
12
Auto-Negotiation enable.
When set, Auto-Negotiation process is enabled. When reset, Auto-Negotiation process is
disabled.
PWRD
11
Power down.
This bit is fixed at the value of 0. The IXF1002 GPCS does not support the power down
function.
ISLT
10
Isolate.
This bit is fixed at the value of 0. The IXF1002 GPCS does not support the isolate function.
A4987-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A
N
E
N
B
L
S
P
E
E
D
_
2
L
P
B
K
R
S
T
S
P
E
E
D
_
1
C
O
L
L
T
S
T
D
U
P
L
E
X
R
E
S
A
N
I
S
L
T
P
W
R
D
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