參數(shù)資料
型號: GCIXF1002ED
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 21/128頁
文件大小: 1262K
代理商: GCIXF1002ED
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
21
3.0
Registers Description
This section describes the IXF1002 registers. Each of the IXF1002 ports includes an independent
register set, enabling maximum flexibility.
The registers in each port are divided into two groups:
Control and status registers (CSRs)
Network statistics counters
3.1
Register Conventions
All the registers in the IXF1002 are implemented in each of its two ports, unless mentioned
otherwise in the text.
In the register description tables throughout this section, the following abbreviations are used to
indicate register access modes:
3.1.1
Access Rules
The following access rules must be followed when accessing registers:
Unlisted addresses are reserved and must not be accessed.
The resolution of the addresses is in bytes.
In 8-bit mode, access to the eight high or low bits of a register will be done directly to the
address of the desired byte.
In 16-bit mode, registers must be accessed with even addresses.
Reserved bits on registers must be written as 0 and are unpredictable on read.
All registers, except PORT_CTL, are writable only when the port is in stop state (as reported in
the interrupt status register
INT_STT), following transmit and receive disable programming.
Multibyte registers are ordered from low to high (the lower address points to the lower byte).
R
=
Readable only.
W
=
Writable only.
R/W
=
Readable and writable.
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