參數(shù)資料
型號: GCIXF1002ED
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 35/128頁
文件大小: 1262K
代理商: GCIXF1002ED
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
35
3.2.3.5
Transmit Threshold Register
Mnemonic: TX_TSHD
Address: 28H
29H
The transmission threshold register handles the packet transmission threshold.
3.2.3.6
Transmit Flow-Control Pause Time Register
Mnemonic: PAUSE_TIME
Address: 2AH
2BH
The transmit flow-control pause time register handles the time field used in the transmitted
flow-control packets.
Access Rules
Register
access
Value
after reset
R/W
1004H
Bit Name
Bit #
Bit Description
Bit Name
Bit #
Bit Description
15:8
RESERVED
TSD
7:0
Packet transmission threshold.
Packet transmission starts when the amount of data in the transmit FIFO is larger than or
equal to the threshold, or the entire packet enters onto the FIFO. The effective threshold in
bytes is equal to 8
×
TSD + 4. If the sum of the effective serial threshold and the effective
parallel threshold bring the system to a deadlock, the transmission can start before
threshold is reached to prevent deadlock. (TSD > 1)
Access Rules
Register
access
R/W
Value
after
reset
0003H
A4977-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSD
A4978-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PTSM
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