參數(shù)資料
型號： GCIXF1002ED
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 42/128頁
文件大?。?/td> 1262K
代理商： GCIXF1002ED
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
42
Datasheet
3.2.4
GMII Management Access Registers
This set of registers is intended to simplify access to the GMII management registers in the PHY,
while working in GMII mode.
In order to access a GMII management register in the PHY, an access command should be written
in the GMII management access register (GMII_MNG_ACC). The IXF1002 carries out the
command and accesses the PHY through the mdc and mdio pins.
In GPCS mode, the set of GMII management registers is provided on the IXF1002 in addresses
50H
–
71GH, and these addresses should be accessed directly.
Note:
These registers are valid only in port 0.
3.2.4.1
GMII Management Access Register
Mnemonic: GMII_MNG_ACC
Address: 4AH
–
4BH (only in port 0)
The GMII Management Access register controls the mdc and mdio I/O pins. Two modes of access
to the PHY are available
Direct access mode: In this mode each of the mdc and mdio I/O pins are set to be input or
output, and can be read or written through this register.
Automatic access mode: This mode is used to access the GMII management register set in the
PHY. The address of the desired PHY and register, and the mode of access (R/W), are defined
in this register. In this mode the IXF1002 will transmit and receive frames to/from the PHY
through the mdc and mdio pins, as defined in the 802.3u standard.
The automatic access will begin after writing a value of 1 to the AMAM bit, if the CPU is in the
16-bit mode, or after a write access to the high byte of this register if the value of the AMAM bit is
1 and the CPU is in 8-bit mode.
Use bits MDC/MDIO as GPIO by writing to register GMII_MNG_ACC.
They are used in the direct access mode as follows:
AMA (bit 0) = 0
MDIO (bit 15) is used to drive the mdio pin (or read from it)
MDC (bit 14) is used to drive the mdio pin
MDCEN (bit 13) enables the mdc pin as an output
RWGMI (bit 12) enables the mdio pin as an output
You can write to the register and drive these pins, and read the pin
’
s value by reading the register
(with enable bits reset).
Access Rules
Register
access
Value after
reset
R/W
0000H
Bit Name
Bit #
Bit Description
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