參數(shù)資料
型號: GCIXF1002ED
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 28/128頁
文件大?。?/td> 1262K
代理商: GCIXF1002ED
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
28
Datasheet
3.2.2.7
Receive Counter Overflow Status Register
Mnemonic: RX_OV_STT
Address: 0EH
11H
The receive counter overflow status register reports overflow events of each receive counter. When
a counter reaches its highest possible value, it will continue to count from zero, and the
corresponding status bit will be set. Reading this register will reset all the bits, and will clear the
interrupt if it was activated.
Bit Name
Bit #
Bit Description
31:20
RESERVED
TX_BD
19
TX_OCT_BAD_CNT counter overflow.
TX_OK
18
TX_OCT_OK_CNT counter overflow.
TX_ER
17
TX_ERR_CNT counter overflow.
TX_PS
16
TX_PAUSE_CNT counter overflow.
TX_1519
15
TX_PKT_1519_CNT counter overflow.
TX_1024
14
TX_PKT_1024_CNT counter overflow.
TX_512
13
TX_PKT_512_CNT counter overflow.
TX_256
12
TX_PKT_256_CNT counter overflow.
TX_128
11
TX_PKT_128_CNT counter overflow.
TX_65
10
TX_PKT_65_CNT counter overflow.
TX_64
9
TX_PKT_64_CNT counter overflow.
8:3
RESERVED
TX_BRD
2
TX_BRD_OK_CNT counter overflow.
TX_MLT
1
TX_MLT_OK_CNT counter overflow.
TX_UNI
0
TX_UNI_OK_CNT counter overflow.
Access Rules
Register
access
R
Value
after
reset
0000H
A4972-02
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
30
31
29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
R
X
_
O
K
R
X
_
B
D
R
X
_
N
_
C
R
R
X
_
B
R
D
R
X
_
M
L
T
R
X
_
U
N
I
R
X
_
S
_
C
R
R
X
_
S
_
O
K
R
X
_
O
V
R
X
_
L
_
O
K
R
X
_
L
C
R
R
X
_
6
4
R
X
_
6
5
R
X
_
1
2
8
R
X
_
2
5
6
R
X
_
5
1
2
R
X
_
1
0
2
4
R
X
_
1
5
1
9
R
X
_
E
R
R
X
_
F
A
L
R
X
_
P
S
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