參數(shù)資料
型號(hào)： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 91/96頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 91 of 96
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit(T3CPM[4]) is provided for a higher level of
protection. When set, a specific sequential value must be
written to T3CLRI to avoid a watchdog reset. The value is a
sequence generated by the 8-bit linear feedback shift register
(LFSR) polynomial = X8 + X6 + X5 + X + 1 (see Figure 38).
The initial value or seed is written to T3ICLR before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload happens.
If it fails to match the expected state, a reset is immediately
generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always guaran-
teed to force an immediate reset. The value of the LFSR cannot
be read; it must be tracked/generated in software.
Example of a sequence:
1.
Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2.
Enter 0xAA in T3CLRI; Timer3 is reloaded.
3.
Enter 0x37 in T3CLRI; Timer3 is reloaded.
4.
Enter 0x6E in T3CLRI; Timer3 is reloaded.
5.
Enter 0x66. 0xDC was expected; the watchdog resets
the chip.
TIMER4—GENERAL-PURPOSE TIMER
Timer4 is a 32-bit general-purpose timer, count down or count
up, with a programmable prescalar. The prescalar source can
be the 32 kHz oscillator, the core clock, or the PLL undivided
output. This source can be scaled by a factor of 1, 16, 256, or
32,768. This gives a minimum resolution of 42 ns when operat-
ing at CD = 0, the core is operating at 41.78 MHz, and with a
prescalar of 1 (ignoring external GPIO).
The counter can be formatted as a standard 32-bit value or as
hours:minutes:seconds:hundredths.
Timer4 has a capture register (T4CAP) that can be triggered by
a selected IRQ’s source initial assertion. When triggered, the
current timer value is copied to T4CAP, and the timer keeps
running. This feature can be used to determine the assertion of
an event with increased accuracy.
The Timer4 interface consists of five MMRS.
T4LD, T4VAL, and T4CAP are 32-bit registers and hold
32-bit unsigned integers. T4VAL and T4CAP are read only.
T4ICLR is an 8-bit register. Writing any value to this
register clears the Timer1 interrupt.
T4CON is the configuration MMR.
Note that if the part is in a low power mode, and Timer4 is
clocked from the GPIO or oscillator source, then Timer4
continues to operate.
Timer4 reloads the value from T4LD either when Timer 4
overflows or immediately when T4CLRI is written.
Table 169. Timer4 Load Registers
Name
Address
Default Value
Access
T4LD
0xFFFF0380
0x00000
R/W
T4LD is a 32-bit register, which holds the 32-bit value that is
loaded into the counter.
Table 170. Timer4 Clear Register
Name
Address
Default Value
Access
T4CLRI
0xFFFF038C
0x00
W
This 8-bit, write only MMR is written (with any value) by user
code to refresh (reload) Timer4.
Table 171. Timer4Value Register
Name
Address
Default Value
Access
T4VAL
0xFFFF0384
0x0000
R
T4VAL is a 32-bit register that holds the current value of
Timer4.
Table 172. Timer4 Capture Register
Name
Address
Default Value
Access
T4CAP
0xFFFF0390
0x00
R
This is a 32-bit register that holds the 32-bit value captured by
an enabled IRQ event.
Table 173. Timer4 Control Register
Name
Address
Default Value
Access
T4CON
0xFFFF0388
0x0000
R/W
This 32-bit MMR configures the mode of operation of Timer4.
08
755-
03
9
CLOCK
QD
4
QD
5
QD
3
QD
7
QD
6
QD
2
QD
1
QD
0
Figure 38. 8-Bit LFSR
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