參數(shù)資料
型號： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 80/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 81 of 96
IRQSTAN Register
If IRQCONN[0] is asserted and IRQVEC is read, then one of
these bits is asserted. The bit that asserts depends on the prior-
ity of the IRQ. For example, if the IRQ is of Priority 0 then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must
be cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
IRQSTAN
Address:
0xFFFF003C
Default Value:
0x00000000
Access:
Read and write
Table 137. IRQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
FIQVEC
Address:
0xFFFF011C
Default Value:
0x00000000
Access:
Read only
Table 138. FIQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31:23
Read only
0
Always read as 0.
22:7
R/W
0
IRQBASE register value.
6:2
0
Highest priority FIQ source. This is
a value between 0 to 27, which
represents the possible interrupt
sources. For example, if the
highest currently active FIQ is
Timer1, then these bits are 00011.
1:0
Reserved
0
Reserved bits.
FIQSTAN Register
If IRQCONN[1] is asserted and FIQVEC is read then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. For example, if the FIQ is of Priority 0, then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit as a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08 and writing 0xFF a second time
changes the register to 0x00.
Name:
FIQSTAN
Address:
0xFFFF013C
Default Value:
0x00000000
Access:
Read and write
Table 139. FIQSTAN MMR Bit Designations
Bit
Name
Description
31:8
Reserved
These bits are reserved and should not be
written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
External Interrupts (IRQ0 to IRQ5)
The ADuC7122 provides up to six external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, the appropriate bit must
first be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
IRQCONE
Address:
0xFFFF0034
Default Value:
0x00000000
Access:
Read and write
相關(guān)PDF資料
PDF描述
EVAL-ADUC7124QSPZ BOARD EVALUATION FOR ADUC7124
ECM30DCWN CONN EDGECARD 60POS DIP .156 SLD
EVAL-ADUC7121QSPZ BOARD EVALUATION FOR ADUC7121
EVAL-ADUC7126QSPZ BOARD EVALUATION FOR ADUC7126
REC5-243.3SRWZ/H4/A CONV DC/DC 5W 9-36VIN 3.3VOUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADUC7124QSPZ 功能描述:BOARD EVALUATION FOR ADUC7124 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
EVAL-ADUC7126QSPZ 功能描述:BOARD EVALUATION FOR ADUC7126 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
EVAL-ADUC7128QSPZ 功能描述:KIT DEV FOR ADUC7128 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
EVAL-ADUC7128QSPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC
EVAL-ADUC7129QSPZ 制造商:Analog Devices 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*