參數(shù)資料
型號： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 41/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 46 of 96
OSCILLATOR AND PLL—POWER CONTROL
The ADuC7122 integrates a 32.768 kHz oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple (1275) of the
internal oscillator to provide a stable 41.78 MHz clock for the
system. The core can operate at this frequency or at binary
submultiples of it to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core
clock frequency can be output on the ECLK pin as described in
Figure 31. Note that when the ECLK pin is used to output the
core clock, the output signal is not buffered and is not suitable
for use as a clock source to an external device without an
external buffer.
A power-down mode is available on the ADuC7122.
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 75) and
POWCON (see Table 76). PLLCON controls the operating
mode of the clock system, and POWCON controls the core
clock frequency and the power-down mode.
0
8755-
032
AT POWER-UP
41.78MHz
OCLK 32.768kHz
WATCHDOG
TIMER
INT. 32kHz1
OSCILLATOR
CRYSTAL
OSCILLATOR
TIMERS
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XTALO
XTALI
XCLK2
ECLK3
NOTES
1. 32.768kHz ± 3%.
2. TO USE THE SECONDARY FUNCTION
OF P1.4 AS XCLK, PLLCON BITS[1:0]
MUST EQUAL 11.
3. WHEN THE SECONDARY FUNCTION
FOR P1.4 IS SET TO 2 (THAT IS, GP1CON[17:16] = 10),
THE ECLK FUNCTION IS SELECTED BY DEFAULT.
Figure 31. Clocking System
EXTERNAL CRYSTAL SELECTION
To switch to an external crystal, use the following procedure:
1.
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
2.
Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3.
Force the part into nap mode by following the correct write
sequence to the POWCON register.
4.
When the part is interrupted from nap mode by the Timer2
interrupt source, the clock source has switched to the
external clock.
Example Source Code
T2LD = 5;
T2CON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
// Set Core into Nap mode
POWKEY2 = 0xF4;
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
EXTERNAL CLOCK SELECTION
To switch to an external clock on P1.4, configure P1.4 in
Mode 2. The external clock can be up to 41.78 MHz, providing
the tolerance is 1%.
Example Source Code
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;
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