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參數(shù)資料
型號(hào)： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 63/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 66 of 96
Bit
Name
Description
7
I2CGC
I2C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type.
If the command received is a reset command, then all registers return to their default state.
If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can
be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
6
I2CSBUSY
I2C slave busy status bit.
Set to 1 when the slave receives a start condition.
Cleared by hardware if the received address does not match any of the I2CxIDx registers, if the slave device receives
a stop condition, or if a repeated start address does not match any of the I2CxIDx registers.
5
I2CSNA
I2C slave NACK data bit.
This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if NACK is returned
because there is no data in the Tx FIFO or if the I2CNACKEN bit is set in the I2CxSCTL register.
This bit is cleared in all other conditions.
4
I2CSRxFO
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
3
I2CSRXQ
I2C slave receive request bit.
This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in
I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
2
I2CSTXQ
I2C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the read bit
transmission.
This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
1
I2CSTFE
I2C slave FIFO underflow status bit.
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the
rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
0
I2CETSTA
I2C slave early transmit FIFO status bit.
If the I2CSETEN bit in I2CxSCTL = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL = 1, this bit goes high just after the positive edge of SCL during the write bit
transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
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