參數(shù)資料
型號： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 75/96頁
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 77 of 96
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI core. The four 32-bit registers dedicated to IRQ
are IRQSIG, IRQEN, IRQCLR, and IRQSTA.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only.
IRQSIG Register
Name:
IRQSIG
Address:
0xFFFF0004
Default Value:
0x00000000
Access:
Read only
IRQEN
IRQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled to
create an IRQ exception. When a bit is set to 0, the correspond-
ing source request is disabled or masked, which does not create
an IRQ exception. The IRQEN register cannot be used to disable
an interrupt.
IRQEN Register
Name:
IRQEN
Address:
0xFFFF0008
Default Value:
0x00000000
Access:
Read/write
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
IRQCLR Register
Name:
IRQCLR
Address:
0xFFFF000C
Default Value:
0x00000000
Access:
Write only
IRQSTA
IRQSTA is a read-only register that provides the current enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
IRQSTA Register
Name:
IRQSTA
Address:
0xFFFF0000
Default Value:
0x00000000
Access:
Read only
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN.
Likewise, a bit set to 1 in IRQEN clears, as a side effect, the
same bit in FIQEN. An interrupt source can be disabled in both
IRQEN and FIQEN masks.
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal, the corresponding bit in
the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
FIQSIG Register
Name:
FIQSIG
Address:
0xFFFF0104
Default Value:
0x00000000
Access:
Read only
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