參數(shù)資料
型號: EVAL-ADUC7122QSPZ
廠商: Analog Devices Inc
文件頁數(shù): 25/96頁
文件大小: 0K
描述: BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源: EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
類型: MCU
適用于相關(guān)產(chǎn)品: ADUC7122
所含物品:
ADuC7122
Rev. 0 | Page 31 of 96
Table 28. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00)
Bit
Value
Description
31:16
These bits are reserved.
15
Positive ADC buffer bypass.
0
Set to 0 by the user to enable the positive ADC buffer.
1
Set to 1 by the user to bypass the positive ADC buffer.
14
Negative ADC buffer bypass.
0
Set to 0 by the user to enable the negative ADC buffer.
1
Set to 1 by the user to bypass the negative ADC buffer.
13:11
ADC clock speed (fADC = fCORE, conversion = 19 ADC clocks + acquisition time).
000
fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz.
001
fADC/2 (default value).
010
fADC/4.
011
fADC/8.
100
fADC/16.
101
fADC/32.
10:8
ADC acquisition time (number of ADC clocks).
000
2 clocks.
001
4 clocks.
010
8 clocks (default value).
011
16 clocks.
100
32 clocks.
101
64 clocks.
7
Enable conversion.
1
Set by user to 1 to enable conversion mode.
0
Cleared by user to 0 to disable conversion mode.
6
Reserved. This bit should be set to 0 by the user.
5
ADC power control.
1
Set by user to 1 to place the ADC in normal mode. The ADC must be powered up for at least 5 μs before it converts correctly.
0
Cleared by user to 0 to place the ADC in power-down mode.
4:3
Conversion mode.
00
Single-ended mode.
01
Differential mode.
10
Pseudo differential mode.
11
Reserved.
2:0
Conversion type.
000
Enable CONVST pin as a conversion input.
001
Enable Timer1 as a conversion input.
010
Enable Timer0 as a conversion input.
011
Single software conversion. Automatically set to 000 after conversion.
100
Continuous software conversion.
101
PLA conversion.
110
Reserved
Other
Reserved.
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