參數(shù)資料
型號： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 71/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 73 of 96
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7122 integrates a fully programmable logic array
(PLA) that consists of two, independent but interconnected
PLA blocks. Each block consists of eight PLA elements, giving
each part a total of 16 PLA elements.
Each PLA element contains a two-input look-up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 35.
0
87
55
-03
6
4
2
0
1
3
A
B
LOOKUP
TABLE
Figure 35. PLA Element
In total, 32 GPIO pins are available on each ADuC7122 for the
PLA. These include 16 input pins and 16 output pins that need to
be configured in the GPxCON register as PLA pins before using
the PLA. Note that the comparator output is also included as
one of the 16 input pins.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONVST signal of the ADC, to an MMR, or to any of the 16
PLA output pins.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed back to Input 0 of
Mux 0 of Element 0 (Block 0)
Output of Element 7 (Block 0) can be fed back to the Input 0
of Mux 0 of Element 8 (Block 1)
Table 113. Element Input/Output
PLA Block 0
PLA Block 1
Element
Input
Output
Element
Input
Output
0
P2.7
P3.0
8
P1.4
P3.4
1
P2.2
P3.1
9
P1.5
P3.5
2
P0.6
P3.2
10
P0.5
P3.6
3
P0.7
P3.3
11
P0.4
P3.7
4
P0.1
P1.7
12
P2.1
P0.3
5
P0.0
P1.6
13
P2.0
P0.2
6
P1.1
P2.5
14
P2.3
P1.3
7
P1.0
P2.4
15
P2.6
P1.2
PLA MMRs Interface
The PLA peripheral interface consists of the 21 MMRs
Table 114. PLAELMx Registers
Name
Address
Default Value
Access
PLAELM0
0xFFFF0B00
0x0000
R/W
PLAELM1
0xFFFF0B04
0x0000
R/W
PLAELM2
0xFFFF0B08
0x0000
R/W
PLAELM3
0xFFFF0B0C
0x0000
R/W
PLAELM4
0xFFFF0B10
0x0000
R/W
PLAELM5
0xFFFF0B14
0x0000
R/W
PLAELM6
0xFFFF0B18
0x0000
R/W
PLAELM7
0xFFFF0B1C
0x0000
R/W
PLAELM8
0xFFFF0B20
0x0000
R/W
PLAELM9
0xFFFF0B24
0x0000
R/W
PLAELM10
0xFFFF0B28
0x0000
R/W
PLAELM11
0xFFFF0B2C
0x0000
R/W
PLAELM12
0xFFFF0B30
0x0000
R/W
PLAELM13
0xFFFF0B34
0x0000
R/W
PLAELM14
0xFFFF0B38
0x0000
R/W
PLAELM15
0xFFFF0B3C
0x0000
R/W
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the look-up table, and bypass/use the flip-flop. See
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