參數(shù)資料
型號(hào)： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/96頁
文件大小： 0K
描述： BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關(guān)產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 40 of 96
Table 57. FEE0PRO and FEE0HID MMR Bit Designations
Bit
Description
31
Read protection.
Cleared by the user to protect Block 0.
Set by the user to allow reading of Block 0.
30:0
Write protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 3 to Page 0.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
Table 58. FEE1PRO and FEE1HID MMR Bit Designations
Bit
Description
31
Read protection.
Cleared by the user to protect Block 1.
Set by the user to allow reading of Block 1.
30
Write protection for Page 127 to Page 120.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
29:0
Write protection for Page 119 to Page 116 and for Page 3 to Page 0.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing the pages.
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution of applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE), one
cycle to execute the instruction and two cycles to obtain the
32-bit data from Flash/EE. A control flow instruction, such as a
branch instruction, takes one cycle to fetch, but it also takes
two cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 23 ns, execution from Flash/EE cannot be completed in
one cycle (contrary to a SRAM fetch, which can be completed in
a single cycle when CD bits = 0). Dependent on the instruction,
some dead times may be required before accessing data for any
value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In Thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter and
then four cycles are needed to fill the pipeline. A data processing
instruction involving only core registers does not require any
extra clock cycles, but if it involves data in Flash/EE, an extra
clock cycle is needed to decode the address of the data and two
cycles to obtain the 32-bit data from Flash/EE. An extra cycle
must also be added before fetching another instruction. Data
transfer instructions are more complex and are summarized in
Table 59. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time
Data Access
Dead
Time
LD
2/1
1
2
1
LDH
2/1
1
LDM/PUSH
2/1
N
2 × N
N
STR
2/1
1
2 × 20 μs
1
STRH
2/1
1
20 μs
1
STRM/POP
2/1
N
2 × N × 20 μs
N
With 1 < N ≤ 16, N is the number of bytes of data to load or
store in the multiple load/store instruction. The SWAP instruction
combines an LD and STR instruction with only one fetch,
giving a total of eight cycles plus 40 μs.
相關(guān)PDF資料
PDF描述
EVAL-ADUC7124QSPZ BOARD EVALUATION FOR ADUC7124
ECM30DCWN CONN EDGECARD 60POS DIP .156 SLD
EVAL-ADUC7121QSPZ BOARD EVALUATION FOR ADUC7121
EVAL-ADUC7126QSPZ BOARD EVALUATION FOR ADUC7126
REC5-243.3SRWZ/H4/A CONV DC/DC 5W 9-36VIN 3.3VOUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADUC7124QSPZ 功能描述:BOARD EVALUATION FOR ADUC7124 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
EVAL-ADUC7126QSPZ 功能描述:BOARD EVALUATION FOR ADUC7126 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
EVAL-ADUC7128QSPZ 功能描述:KIT DEV FOR ADUC7128 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
EVAL-ADUC7128QSPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC
EVAL-ADUC7129QSPZ 制造商:Analog Devices 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*