參數(shù)資料
型號(hào): EVAL-ADUC7122QSPZ
廠商: Analog Devices Inc
文件頁數(shù): 70/96頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADUC7122
設(shè)計(jì)資源: EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
類型: MCU
適用于相關(guān)產(chǎn)品: ADUC7122
所含物品:
ADuC7122
Rev. 0 | Page 72 of 96
Bit
Name
Description
8
SPIROW
SPIRX overflow overwrite enable.
Set by the user, the valid data in the Rx register is overwritten by the new serial byte received.
Cleared by the user, the new serial byte received is discarded.
7
SPIZEN
SPI transmit zeros when the Tx FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
6
SPITMDE
SPI transfer and interrupt mode.
Set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
5
SPILF
LSB first transfer enable bit.
Set by the user, the LSB is transmitted first
Cleared by the user, the MSB is transmitted first.
4
SPIWOM
SPI wired or mode enable bit
Set to 1 to enable open-drain data output enable. External pull-ups required on data out pins.
Cleared for normal output levels.
3
SPICPO
Serial clock polarity mode bit.
Set by the user, the serial clock idles high.
Cleared by the user, the serial clock idles low.
2
SPICPH
Serial clock phase mode bit.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
1
SPIMEN
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
0
SPIEN
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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