參數(shù)資料
型號： EVAL-ADUC7122QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/96頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC7122
設計資源： EVAL-ADUC7122 Schematic
ADUC7122 Gerber Files
ADUC7122 BOM
標準包裝： 1
系列： MicroConverter® ADuC7xxx
類型： MCU
適用于相關產(chǎn)品： ADUC7122
所含物品： 板
ADuC7122
Rev. 0 | Page 29 of 96
All the controls are independently set through register bits to
give maximum flexibility to the user. Typically, users must set
the following:
1.
Select PADCxP as the PGA input. Enable the PADCxN
buffer and optionally disable the PADCxP input buffer.
2.
Set the proper gain value for the PGA. Bypass the
PADCxN buffer if a grounded signal is required.
3.
Set the ADC to pseudo differential mode and start the
conversion.
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADCDAT register.
The top four bits are the sign bits, and the 12-bit result is placed
from Bit 16 to Bit 27, as shown in Figure 15. Note that in fully
differential mode, the result is represented in twos complement
format, and in pseudo differential and single-ended mode, the
result is represented in straight binary format.
SIGN BITS
12-BIT ADC RESULT
31
27
16 15
0
0
875
5-
01
5
Figure 15. ADC Result Format
Calibration
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield opti-
mum performance in terms of end-point errors and linearity for
standalone operation of the part (see the General Description
section). If system calibration is required, it is possible to mod-
ify the default offset and gain coefficients to improve end-point
errors, but note that any modification to the factory-set ADCOF
and ADCGN values can degrade ADC linearity performance.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF
until the ADC result (ADCDAT) reads Code 0 to Code 1. If
the ADCDAT value is greater than 1, ADCOF should be decre-
mented until ADCDAT reads Code 0 to Code 1. Offset error
correction is performed digitally and has a resolution of 0.25 LSB
and a range of ±3.125% of VREF.
For system gain error correction, the ADC channel input stage
must be tied to VREF. A continuous software ADC conversion
loop must be implemented to modify the value in ADCGN
until ADCDAT reads Code 4094 to Code 4095. If the ADCDAT
value is less than 4094, ADCGN should be incremented until
ADCDAT reads Code 4094 to Code 4095. Similar to the offset
calibration, the gain calibration resolution is 0.25 LSB with a
range of ±3% of VREF.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA,
multiplied by the sampling frequency (in kHz).
Timing
Figure 16 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clock in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is two. The number of extra clocks (such
as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS.
For conversion on the temperature sensor, the ADC acquisition
time is automatically set to 16 clocks and the ADC clock divider
is set to 32. When using multiple channels, including the
temperature sensor, the timing settings revert back to the user-
defined settings after reading the temperature sensor channel.
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONVST
ADCBUSY
ADCDAT
08
755-
016
Figure 16. ADC Timing
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