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參數(shù)資料
| 型號： | DSP56367UM |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 56/100頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | DSP56367UM |
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Parallel Host Interface (HDI08) Timing
DSP56367 Technical Data, Rev. 2.1
3-32
Freescale Semiconductor
332
HCS assertion to output data valid
—
—
19.1
ns
333
HCS hold time after data strobe deassertion
9
—
0.0
—
ns
334
Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
—
4.7
—
ns
335
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
—
3.3
—
ns
336
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
strobe assertion
9
Read
Write
—
0
4.7
—
—
ns
337
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
deassertion
9
—
3.3
—
ns
338
Delay from read data strobe deassertion to host request assertion for “Last
Data Register” read
4,
5,
10
T
C
6.7
—
ns
339
Delay from write data strobe deassertion to host request assertion for “Last
Data Register” write
5,
8,
10
2
×
T
C
13.4
—
ns
340
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 0)
5,
9, 10
—
—
19.1
ns
341
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 1, open drain Host Request)
5, 9, 10, 11
—
—
300.0
ns
342
Delay from DMA HACK deassertion to HOREQ assertion
For “Last Data Register” read
5
For “Last Data Register” write
5
For other cases
2
×
T
C
+ 19.1
1.5
×
T
C
+ 19.1
32.5
29.2
0.0
—
—
—
ns
343
Delay from DMA HACK assertion to HOREQ deassertion
HROD = 0
5
—
—
20.2
ns
344
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
HROD = 1, open drain Host Request
5,
11
—
—
300.0
ns
1
See Host Port Usage Considerations in the DSP56367 User’s Manual.
2
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3
V
CC
= 1.8 V ± 5%; T
J
= –40°C to +95°C, C
L
= 50 pF
4
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
5
The “l(fā)ast data register” is the register at address $7, which is the last location to be read or written in data transfers.
6
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
7
This timing is applicable only if two consecutive reads from one of these registers are executed.
8
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
Table 3-15 Host Interface (HDI08) Timing
1, 2, 3
(continued)
No.
Characteristics
Expression
150 MHz
Unit
Min
Max
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