參數(shù)資料
型號(hào)： DSP56367UM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁數(shù)： 37/100頁
文件大?。?/td> 1039K
代理商： DSP56367UM
External Memory Expansion Port (Port A)
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-13
104
Address and AA valid to input data valid
t
AA
, t
AC
(WS + 0.75)
×
T
C
5
.0 [WS
≥
2]
—
13.3
ns
105
RD assertion to input data valid
t
OE
(WS + 0.25)
×
T
C
5.0 [WS
≥
2]
—
10.0
ns
106
RD deassertion to data not valid (data hold time)
t
OHZ
0.0
—
ns
107
Address valid to WR deassertion
2
t
AW
(WS + 0.75)
×
T
C
4.0 [WS
≥
2]
14.3
—
ns
108
Data valid to WR deassertion (data setup time)
t
DS
(t
DW
) (WS
0.25)
×
T
C
3.0 [WS
≥
2]
8.7
—
ns
109
Data hold time from WR deassertion
t
DH
1.25
×
T
C
2.0[2
≤
WS
≤
7]
2.25
×
T
C
2.0 [WS
≥
8]
6.3
13.0
—
—
ns
ns
110
WR assertion to data active
—
0.25
×
T
C
3.7 [2
≤
WS
≤
3]
0.25
×
T
C
3.7 [WS
≥
4]
-2.0
-5.4
—
—
ns
ns
111
WR deassertion to data high impedance
—
0.25
×
T
C
+ 0.2 [2
≤
WS
≤
3]
1.25
×
T
C
+ 0.2 [4
≤
WS
≤
7]
2.25
×
T
C
+ 0.2 [WS
≥
8]
—
—
—
1.9
8.5
15.2
ns
ns
ns
112
Previous RD deassertion to data active (write)
—
1.25
×
T
C
4.0 [2
≤
WS
≤
3]
2.25
×
T
C
4.0 [4
≤
WS
≤
7]
3.25
×
T
C
4.0 [WS
≥
8]
4.3
11.0
17.7
—
—
—
ns
ns
ns
113
RD deassertion time
1.75
×
T
C
4.0 [2
≤
WS
≤
7]
2.75
×
T
C
4.0 [WS
≥
8]
7.7
14.3
—
—
ns
ns
114
WR deassertion time
2.0
×
T
C
4.0 [2
≤
WS
≤ 3
]
2.5
×
T
C
4.0 [4
≤
WS
≤
7]
3.5
×
T
C
4.0 [WS
≥
8]
9.3
12.7
19.3
—
—
—
ns
ns
ns
115
Address valid to RD assertion
0.5
×
T
C
2.0
1.3
—
ns
116
RD assertion pulse width
(WS + 0.25)
×
T
C
4.0
11.0
—
ns
117
RD deassertion to address not valid
1.25
×
T
C
2.0 [2
≤
WS
≤
7]
2.25
×
T
C
2.0 [WS
≥
8]
6.3
13.0
—
—
ns
ns
118
TA setup before RD or WR deassertion
3
0.25
×
T
C
+ 2.0
3.7
—
ns
119
TA hold after RD or WR deassertion
0.0
—
ns
1
WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,
for a category of [2
≤
WS
≤
7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise.
2
Timings 100, 107 are guaranteed by design, not tested.
3
In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
Table 3-8 SRAM Read and Write Accesses (continued)
No.
Characteristics
Symbol
Expression
1
150 MHz
Unit
Min
Max
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