參數(shù)資料
型號(hào)： DSP56367UM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 40/100頁(yè)
文件大?。?/td> 1039K
代理商： DSP56367UM
External Memory Expansion Port (Port A)
DSP56367 Technical Data, Rev. 2.1
3-16
Freescale Semiconductor
Table 3-9 DRAM Page Mode Timings, Three Wait States
1, 2, 3
No.
Characteristics
Symbol
Expression
4
100 MHz
Unit
Min
Max
131
Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
t
PC
2
×
T
C
1.25
×
T
C
20.0
12.5
—
—
ns
132
CAS assertion to data valid (read)
t
CAC
2
×
T
C
7.0
—
13.0
ns
133
Column address valid to data valid (read)
t
AA
3
×
T
C
7.0
—
23.0
ns
134
CAS deassertion to data not valid (read hold time)
t
OFF
0.0
—
ns
135
Last CAS assertion to RAS deassertion
t
RSH
2.5
×
T
C
4.0
21.0
—
ns
136
Previous CAS deassertion to RAS deassertion
t
RHCP
4.5
×
T
C
4.0
41.0
—
ns
137
CAS assertion pulse width
t
CAS
2
×
T
C
4.0
16.0
—
ns
138
Last CAS deassertion to RAS assertion
5
BRW[1:0] = 00, 01— not applicable
BRW[1:0] = 10
BRW[1:0] = 11
t
CRP
4.75
×
T
C
6.0
6.75
×
T
C
6.0
41.5
61.5
—
—
ns
139
CAS deassertion pulse width
t
CP
1.5
×
T
C
4.0
11.0
—
ns
140
Column address valid to CAS assertion
t
ASC
T
C
4.0
6.0
—
ns
141
CAS assertion to column address not valid
t
CAH
2.5
×
T
C
4.0
21.0
—
ns
142
Last column address valid to RAS deassertion
t
RAL
4
×
T
C
4.0
36.0
—
ns
143
WR deassertion to CAS assertion
t
RCS
1.25
×
T
C
4.0
8.5
—
ns
144
CAS deassertion to WR assertion
t
RCH
0.75
×
T
C
4.0
3.5
—
ns
145
CAS assertion to WR deassertion
t
WCH
2.25
×
T
C
4.2
18.3
—
ns
146
WR assertion pulse width
t
WP
3.5
×
T
C
4.5
30.5
—
ns
147
Last WR assertion to RAS deassertion
t
RWL
3.75
×
T
C
4.3
33.2
—
ns
148
WR assertion to CAS deassertion
t
CWL
3.25
×
T
C
4.3
28.2
—
ns
149
Data valid to CAS assertion (write)
t
DS
0.5
×
T
C
4.0
1.0
—
ns
150
CAS assertion to data not valid (write)
t
DH
2.5
×
T
C
4.0
21.0
—
ns
151
WR assertion to CAS assertion
t
WCS
1.25
×
T
C
4.3
8.2
—
ns
152
Last RD assertion to RAS deassertion
t
ROH
3.5
×
T
C
4.0
31.0
—
ns
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