
External Memory Expansion Port (Port A)
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-25
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
1, 2
No.
Characteristics
Symbol
Expression
3
100 MHz
Unit
Min
Max
157
Random read or write cycle time
t
RC
16
×
T
C
160.0
—
ns
158
RAS assertion to data valid (read)
t
RAC
8.25
×
T
C
5.7
—
76.8
ns
159
CAS assertion to data valid (read)
t
CAC
4.75
×
T
C
5.7
—
41.8
ns
160
Column address valid to data valid (read)
t
AA
5.5
×
T
C
5.7
—
49.3
ns
161
CAS deassertion to data not valid (read hold time)
t
OFF
0.0
0.0
—
ns
162
RAS deassertion to RAS assertion
t
RP
6.25
×
T
C
4.0
58.5
—
ns
163
RAS assertion pulse width
t
RAS
9.75
×
T
C
4.0
93.5
—
ns
164
CAS assertion to RAS deassertion
t
RSH
6.25
×
T
C
4.0
58.5
—
ns
165
RAS assertion to CAS deassertion
t
CSH
8.25
×
T
C
4.0
78.5
—
ns
166
CAS assertion pulse width
t
CAS
4.75
×
T
C
4.0
43.5
—
ns
167
RAS assertion to CAS assertion
t
RCD
3.5
×
T
C
±
2
33.0
37.0
ns
168
RAS assertion to column address valid
t
RAD
2.75
×
T
C
±
2
25.5
29.5
ns
169
CAS deassertion to RAS assertion
t
CRP
7.75
×
T
C
4.0
73.5
—
ns
170
CAS deassertion pulse width
t
CP
6.25
×
T
C
– 6.0
56.5
—
ns
171
Row address valid to RAS assertion
t
ASR
6.25
×
T
C
4.0
58.5
—
ns
172
RAS assertion to row address not valid
t
RAH
2.75
×
T
C
4.0
23.5
—
ns
173
Column address valid to CAS assertion
t
ASC
0.75
×
T
C
4.0
3.5
—
ns
174
CAS assertion to column address not valid
t
CAH
6.25
×
T
C
4.0
58.5
—
ns
175
RAS assertion to column address not valid
t
AR
9.75
×
T
C
4.0
93.5
—
ns
176
Column address valid to RAS deassertion
t
RAL
7
×
T
C
4.0
66.0
—
ns
177
WR deassertion to CAS assertion
t
RCS
5
×
T
C
3.8
46.2
—
ns
178
CAS deassertion to WR
4
assertion
t
RCH
1.75
×
T
C
– 3.7
13.8
—
ns
179
RAS deassertion to WR
4
assertion
t
RRH
0.25
×
T
C
2.0
0.5
—
ns
180
CAS assertion to WR deassertion
t
WCH
6
×
T
C
4.2
55.8
—
ns
181
RAS assertion to WR deassertion
t
WCR
9.5
×
T
C
4.2
90.8
—
ns
182
WR assertion pulse width
t
WP
15.5
×
T
C
4.5
150.5
—
ns