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參數(shù)資料
| 型號： | DSP56367UM |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 32/100頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | DSP56367UM |
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Reset, Stop, Mode Select, and Interrupt Timing
DSP56367 Technical Data, Rev. 2.1
3-8
Freescale Semiconductor
21
Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts
5, 6, 7
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS
≥
4
(WS + 3.5)
×
T
C
– 10.94
N/A
1.75
×
T
C
– 4.0
2.75
×
T
C
– 4.0
—
—
—
—
Note 8
Note 8
Note 8
Note 8
ns
22
Synchronous int setup time from IRQs NMI assertion to the
CLKOUT trans.
0.6
×
T
C
– 0.1
3.9
—
ns
23
Synch. int delay time from the CLKOUT trans2 to the first
external address out valid caused by first inst fetch
Minimum
Maximum
9.25
×
T
C
+ 1.0
24.75
×
T
C
+ 5.0
62.7
—
—
170.0
ns
24
Duration for IRQA assertion to recover from Stop state
0.6
×
T
C
0.1
3.9
—
ns
25
Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)
2, 8
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No
Stop Delay)
PLC
×
ET
C
×
PDF + (128 K
PLC/2)
×
T
C
PLC
×
ET
C
×
PDF + (23.75
+/- 0.5)
×
T
C
(8.25
±
0.5)
×
T
C
—
—
51.7
—
—
58.3
ms
ms
ns
26
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)
2, 8
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (implies no
Stop delay)
PLC
×
ET
C
×
PDF + (128 K
PLC/2)
×
T
C
PLC
×
ET
C
×
PDF + (20.5
+/- 0.5)
×
T
C
5.5
×
T
C
—
—
36.7
—
—
—
ms
ms
ns
27
Interrupt Requests Rate
HDI08, ESAI, ESAI_1, SHI, DAX, Timer
DMA
IRQ, NMI (edge trigger)
IRQ (level trigger)
12T
C
8T
C
8T
C
12T
C
—
—
—
—
80.0
53.0
53.0
80.0
ns
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
1
(continued)
No.
Characteristics
Expression
Min
Max
Unit
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|---|---|
| DSP56371 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371AF180 | 制造商:Freescale Semiconductor 功能描述: |
| DSP56371D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DSP56371UM |
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