參數(shù)資料
型號: DS2151
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁數(shù): 7/51頁
文件大?。?/td> 1100K
代理商: DS2151
DS2151Q
7 of 51
DS2151Q REGISTER MAP
(continued)
63
64
65
66
67
68
69
6A
6B
6C
R
R
R
R
R
R
R
R
R
Receive Signaling Register 4.
Receive Signaling Register 5.
Receive Signaling Register 6.
Receive Signaling Register 7.
Receive Signaling Register 8.
Receive Signaling Register 9.
Receive Signaling Register 10.
Receive Signaling Register 11.
Receive Signaling Register 12.
Receive Channel Blocking
Register 1.
Receive Channel Blocking
Register 2.
Receive Channel Blocking
Register 3.
Interrupt Mask Register 2.
73
74
75
76
77
78
79
7A
7B
7C
R/W Transmit Signaling Register 4.
R/W Transmit Signaling Register 5.
R/W Transmit Signaling Register 6.
R/W Transmit Signaling Register 7.
R/W Transmit Signaling Register 8.
R/W Transmit Signaling Register 9.
R/W Transmit Signaling Register 10.
R/W Transmit Signaling Register 11.
R/W Transmit Signaling Register 12.
R/W Line Interface Control Register.
R/W
6D
R/W
7D
R/W Test Register. (2)
6E
R/W
7E
R/W Transmit FDL Register.
6F
R/W
7F
R/W Interrupt Mask Register 1.
NOTES:
1.
Address 25 also contains Multiframe Out of Sync Count Register 1.
2.
The Test Register is used only by the factory; this register must be cleared (set to all 0s) on power-up
initialization to insure proper operation.
2.0
The DS2151Q is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2151Q can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS2151Q saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the
PARALLEL PORT
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