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參數(shù)資料
| 型號(hào)： | DS2151 |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151 |
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DS2151Q
25 of 51
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2151Q has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit
position, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
DS2151Q will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled
via IMR2.4, the
INT2
pin will toggle low indicating that the buffer has filled and needs to be read. The
user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the
INT2
pin will be toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore
the FDL or Fs pattern until an important event occurs.
The DS2151Q also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1s should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2151Q
will automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will
automatically remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not
removed. The CCR2.0 bit should always be set to a 1 when the DS2151Q is extracting the FDL. More
on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate Application Note.
Also, contact the factory for C code software that implements both ANSI T1.403 and AT&T
TR54016.
RFDL: RECEIVE FDL REGISTER
(Address=28 Hex)
(MSB)
RFDL7
RFDL6
RFDL5
(LSB)
RFDL0
RFDL4
RFDL3
RFDL2
RFDL1
SYMBOL
RFDL7
POSITION
RFDL.7
NAME AND DESCRIPTION
MSB of the Received FDL Code
RFDL0
RFDL.0
LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1
(Address=29 Hex)
RFDLM2: RECEIVE FDL MATCH REGISTER 2
(Address=2A Hex)
(MSB)
RFDL7
RFDL6
RFDL5
(LSB)
RFDL0
RFDL4
RFDL3
RFDL2
RFDL1
SYMBOL
RFDL7
POSITION
RFDL.7
NAME AND DESCRIPTION
MSB of the FDL Match Code
RFDL0
RFDL.0
LSB of the FDL Match Code
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS2151DK | 功能描述:KIT TRANSCEIVER T1 DESIGN DS2151 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2151K | 功能描述:IC TXRX T1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2151Q | 制造商:DAL 功能描述:2151 DAL'95 NOTES 制造商:Maxim Integrated Products 功能描述:PCM TRANSCEIVER, Single, T-1(DS1), 44 Pin, Plastic, PLCC |
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
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