參數(shù)資料
型號(hào): DS2151
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁(yè)數(shù): 23/51頁(yè)
文件大?。?/td> 1100K
代理商: DS2151
DS2151Q
23 of 51
B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter
is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1
(Address=23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2
(Address=24 Hex)
(MSB)
LCV15
LCV14
LCV13
LCV12
LCV7
LCV6
LCV5
LCV4
(LSB)
LCV8
LCV0
LCV11
LCV3
LCV10
LCV2
LCV9
LCV1
LCVCR1
LCVCR2
SYMBOL
LCV15
POSITION
LCVCR1.7
NAME AND DESCRIPTION
MSB of the 16-bit code violation count
LCV0
LCVCR2.0
LSB of the 16-bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS
Table 5-1
COUNT EXCESSIVE
0S
(RCR1.7)
no
no
yes
no
no
yes
yes
yes
B8ZS ENABLED
(CCR2.2)
WHAT IS COUNTED IN THE
LCVCRs
BPVs
BPVs + 16 consecutive 0s
BPVs (B8ZS code words not counted)
BPVs + 8 consecutive 0s
5.2 Path Code Violation Count Register (PCVCR)
When the receive side of the DS2151Q is set to operate in the ESF framing mode (CCR2.3=1), PCVCR
will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to
operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing
bit position. Via the RCR2.1 bit, the DS2151Q can be programmed to also report errors in the Fs framing
bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions.
See Table 5-2 for a detailed description of exactly what errors the PCVCR counts.
PCVCR1: PATH VIOLATION COUNT REGISTER 1
(Address=25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2
(Address=26 Hex)
(MSB)
(note 1)
CRC/FB7
(LSB)
CRC/FB8
CRC/FB0
(note 1)
CRC/FB6
(note 1)
CRC/FB5
(note 1)
CRC/FB4
CRC/FB11
CRC/FB3
CRC/FB10
CRC/FB2
CRC/FB9
CRC/FB1
PCVCR1
PCVCR2
SYMBOL
CRC/FB11
POSITION
PCVCR1.3
NAME AND DESCRIPTION
MSB of the 12-Bit CRC6 Error or Frame Bit Error
Count (note 2)
CRC/FB0
PCVCR2.0
LSB of the 12-Bit CRC6 Error or Frame Bit Error Count
(note 2)
NOTES:
1.
The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register.
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