參數(shù)資料
型號(hào): DS2151
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁(yè)數(shù): 32/51頁(yè)
文件大?。?/td> 1100K
代理商: DS2151
DS2151Q
32 of 51
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS
(Address=2D to 2F Hex)
(MSB)
CH8
CH7
CH6
CH5
CH4
CH16
CH15
CH14
CH13
CH12
CH24
CH23
CH22
CH21
CH20
(LSB)
CH1
CH9
CH17
CH3
CH11
CH19
CH2
CH10
CH18
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)
SYMBOL
CH24
POSITION
RMR3.7
NAME AND DESCRIPTION
Receive Channel Blocking Registers
.
0=do not affect the receive data associated with this
channel
CH1
RMR1.0
1=replace the receive data associated with this channel
with either the idle code or the digital milliwatt code
(depends on the RCR2.7 bit)
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2151Q contains three sections; (1) the receiver which handles clock
and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR),
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER
(Address=7C Hex)
(MSB)
L2
L1
L0
EGL
(LSB)
TPD
JAS
JABDS
DJA
LICR
SYMBOL
POSITION
LICR.7
NAME AND DESCRIPTION
Line Build Out Select Bit 2.
Sets the transmitter build
out; see the Table 12-2
L2
L1
LICR.6
Line Build Out Select Bit 1
. Sets the transmitter build
out; see the Table 12-2
L0
LICR.5
Line Build Out Select Bit 0
. Sets the transmitter build
out; see the Table 12-2
EGL
LICR.4
Receive Equalizer Gain Limit
.
0= -36 dB
1= -30 dB
JAS
LICR.3
Jitter Attenuator Select
.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
JABDS
LICR.2
Jitter Attenuator Buffer Depth Select
.
0=128 bits
1=32 bits (use for delay sensitive applications)
DJA
LICR.1
Disable Jitter Attenuator
.
0=jitter attenuator enabled
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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