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參數(shù)資料
| 型號(hào)： | DS2151 |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151 |
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DS2151Q
20 of 51
NOTE:
1.
The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm
detectors should be able to operate properly in the presence of a 10-3 error rate and they should not
falsely trigger on a framed all 1s signal. The blue alarm criteria in the DS2151Q has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS status bit
in detecting a blue alarm.
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard Loop Up or Loop Down codes are being
received by the DS2151Q. When a Loop Up code has been received for 5 seconds, the CPE is expected
to loop the recovered data (without correcting BPVs) back to the source. The Loop Down code indicates
that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS2151Q will detect the Loop Up/Down codes in both framed and unframed circumstances with bit error
rates as high as 10**-2. The loop code detector has a nominal integration period of 48 ms. Hence, after
about 48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it
is recommended that the software poll the DS2151Q every 100 ms to 500 ms until 5 seconds have elapsed
to insure that the code is continuously present. Once 5 seconds have passed, the DS2151Q should be
taken into or out of loopback via the Remote Loopback (RLB) bit in CCR1.
SR2: STATUS REGISTER 2
(Address=21 Hex)
(MSB)
RMF
TMF
(LSB)
-
SEC
RFDL
TFDL
RMTCH
RAF
SYMBOL
POSITION
SR2.7
NAME AND DESCRIPTION
Receive Multiframe
. Set on receive multiframe boundaries.
RMF
TMF
SR2.6
Transmit Multiframe
. Set on transmit multiframe boundaries.
SEC
SR2.5
One Second Timer
. Set on increments of 1 second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds.
RFDL
SR2.4
Receive FDL Buffer Full
. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
TFDL
SR2.3
Transmit FDL Buffer Empty
. Set when the transmit FDL
buffer (TFDL) empties.
RMTCH
SR2.2
Receive FDL Match Occurrence
. Set when the RFDL
matches either RFDLM1 or RFDLM2.
RAF
SR2.1
Receive FDL Abort
. Set when eight consecutive 1s are
received in the FDL.
-
SR2.0
Not Assigned
. Should be set to 0 when written.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2154L | Enhanced E1 Single Chip Transceiver |
| DS2154LN | Enhanced E1 Single Chip Transceiver |
| DS2154 | WSD 151 SOLDERING STATION 230V UKWSD 151 SOLDERING STATION 230V UK; Frequency, supply max:60Hz; Frequency, supply min:50Hz; Height:101mm; Length:166mm; Power, input:150W; Temperature range:50(degree C) - 550(degree C); Voltage, |
| DS2155 | T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface |
| DS2156 | T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151DK | 功能描述:KIT TRANSCEIVER T1 DESIGN DS2151 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2151K | 功能描述:IC TXRX T1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2151Q | 制造商:DAL 功能描述:2151 DAL'95 NOTES 制造商:Maxim Integrated Products 功能描述:PCM TRANSCEIVER, Single, T-1(DS1), 44 Pin, Plastic, PLCC |
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
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