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參數(shù)資料
| 型號： | DS2151 |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 34/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151 |
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DS2151Q
34 of 51
LBO SELECT IN LICR
Table 12-2
L2
L1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
L0
0
1
0
1
0
1
0
1
LINE BUILD OUT
0 to 133 feet/0 dB
133 to 266 feet
266 to 399 feet
399 to 533 feet
533 to 655 feet
-7.5 dB
-15 dB
-22.5 dB
APPLICATION
DSX-1/CSU
DSX-1
DSX-1
DSX-1
DSX-1
CSU
CSU
CSU
Due to the nature of the design of the transmitter in the DS2151Q, very little jitter (less then 0.005 UIpp
broad-band from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that
they create are independent of the duty cycle of TCLK. The transmitter in the DS2151Q couples to the
T1 transmit twisted pair via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 12-1. In order for
the devices to create the proper waveforms, the transformer used must meet the specifications listed in
Table 12-3.
TRANSFORMER SPECIFICATIONS
Table 12-3
SPECIFICATION
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
RECOMMENDED VALUE
1:1 (receive) and 1:1.15 or 1:1.36 (transmit)
±
5%
600
μ
H minimum
1.0
μ
H maximum
40 pF maximum
1.2 ohms maximum
12.3 JITTER ATTENUATOR
The DS2151Q contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 12-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA-bit in the LICR. In
order for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 12-4
below must be connected to the XTAL1 and XTAL2 pins. The jitter attenuator divides the clock
provided by the 6.176 MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains
very little jitter. Onboard circuitry will pull the crystal (by switching in or out load capacitance) to keep it
long-term averaged to the same frequency as the incoming T1 signal. If the incoming jitter exceeds either
120UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2151Q will divide the
attached crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When
the device divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the
Receive Information Register 2 (RIR2.2).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS2151DK | 功能描述:KIT TRANSCEIVER T1 DESIGN DS2151 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2151K | 功能描述:IC TXRX T1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151Q | 制造商:DAL 功能描述:2151 DAL'95 NOTES 制造商:Maxim Integrated Products 功能描述:PCM TRANSCEIVER, Single, T-1(DS1), 44 Pin, Plastic, PLCC |
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
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