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參數(shù)資料
| 型號： | DS2151 |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 15/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151 |
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DS2151Q
15 of 51
CCR3: COMMON CONTROL REGISTER 3
(Address=30 Hex)
(MSB)
ESMDM
ESR
P16F
(LSB)
LIRST
RSMS
PDE
TLD
TLU
SYMBOL
ESMDM
POSITION
CCR3.7
NAME AND DESCRIPTION
Elastic Store Minimum Delay Mode.
See Section 10.3 for
details.
0=elastic stores operate at full two-frame depth
1=elastic stores operate at 32-bit depth
ESR
CCR3.6
Elastic Store Reset.
Setting this bit from a 0 to a 1 will force
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent reset.
P16F
CCR3.5
Function of Pin 16
.
0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).
RSMS
CCR3.4
RSYNC Multiframe Skip Control.
Useful in framing format
conversions from D4 to ESF.
0=RSYNC will output a pulse at every multiframe
1=RSYNC will output a pulse at every other multiframe note:
for this bit to have any affect, the RSYNC must be set to output
multiframe pulses (RCR2.4=1 and RCR2.3=0) and the receive
elastic store must be bypassed. (CCR1.2 = 0).
PDE
CCR3.3
Pulse Density Enforcer Enable.
0=disable transmit pulse density enforcer
1=enable transmit pulse density enforcer
TLD
CCR3.2
Transmit Loop Down Code (001)
.
0=transmit data normally
1=replace normal transmitted data with Loop Down code
TLU
CCR3.1
Transmit Loop Up Code (00001)
.
0=transmit data normally
1=replace normal transmitted data with Loop Up code
LIRST
CCR3.0
Line Interface Reset.
Setting this bit from a 0 to a one will
initiate an internal reset that affects the slicer, AGC, clock
recovery state machine and jitter attenuator. Normally this bit is
only toggled on power-up. Must be cleared and set again for a
subsequent reset.
LOOP CODE GENERATION
When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted
payload with either the Loop Up or Loop Down code respectively. The DS2151Q will overwrite the
repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as
long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the same time.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151DK | 功能描述:KIT TRANSCEIVER T1 DESIGN DS2151 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2151K | 功能描述:IC TXRX T1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151Q | 制造商:DAL 功能描述:2151 DAL'95 NOTES 制造商:Maxim Integrated Products 功能描述:PCM TRANSCEIVER, Single, T-1(DS1), 44 Pin, Plastic, PLCC |
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
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