參數(shù)資料
型號(hào): DS2151
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁(yè)數(shù): 22/51頁(yè)
文件大?。?/td> 1100K
代理商: DS2151
DS2151Q
22 of 51
IMR2: INTERRUPT MASK REGISTER 2
(Address=6F Hex)
(MSB)
RMF
TMF
SEC
(LSB)
-
RFDL
TFDL
RMTCH
RAF
SYMBOL
POSITION
IMR2.7
NAME AND DESCRIPTION
Receive Multiframe
.
0=interrupt masked
1=interrupt enabled
RMF
TMF
IMR2.6
Transmit Multiframe
.
0=interrupt masked
1=interrupt enabled
SEC
IMR2.5
One-Second Timer
.
0=interrupt masked
1=interrupt enabled
RFDL
IMR2.4
Receive FDL Buffer Full
.
0=interrupt masked
1=interrupt enabled
TFDL
IMR2.3
Transmit FDL Buffer Empty
.
0=interrupt masked
1=interrupt enabled
RMTCH
IMR2.2
Receive FDL Match Occurrence
.
0=interrupt masked
1=interrupt enabled
RAF
IMR2.1
Receive FDL Abort
.
0=interrupt masked
1=interrupt enabled
-
IMR2.0
Not Assigned.
Should be set to 0 when written to.
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the
CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on one second boundaries as
determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data is
lost. All three counters will saturate at their respective maximum counts and they will not rollover (note:
only the Line Code Violation Count Register has the potential to overflow).
5.1 Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive 0s. See Table 5-1 for details of exactly what the LCVCRs count. If the
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