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參數(shù)資料
| 型號： | DS2151 |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151 |
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DS2151Q
16 of 51
PULSE DENSITY ENFORCER
The SCT always examines both the transmit and receive data streams for violations of the following rules
which are required by ANSI T1.403-199X:
–
no more than 15 consecutive 0s
–
at least N 1s in each and every time window of 8 x (N +1) bits where N=1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively.
When the CCR3.3 is set to 1, the DS2151Q will force the transmitted stream to meet this requirement no
matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0,
since B8ZS encoded data streams cannot violate the pulse density requirements.
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS2151Q should be configured for operation by writing to
all of the internal registers (this includes setting the Test Register to 00Hex) since the contents of the
internal registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to
reset the line interface (it will take the DS2151Q about 40 ms to recover from the LIRST being toggled).
Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 (this step can be
skipped if the elastic stores are disabled).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2151Q:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register 1 (RIR1), and Receive
Information Register 2 (RIR2). When a particular event has occurred (or is occurring), the appropriate bit
in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched
fashion. This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again or if the alarm(s) is still present.
The user will always precede a read of these registers with a write. The byte written to the register will
inform the DS2151Q which bits the user wishes to read and have cleared. The user will write a byte to
one of these four registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions
he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read
register will be updated with current value and the previous value will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that the bit does indeed clear. This second write is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. The write-read-write scheme is unique to the four status registers and it allows an
external microcontroller or microprocessor to individually poll certain bits without disturbing the other
bits in the register. This operation is key in controlling the DS2151Q with higher-order software
languages.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the
INT1
and
INT2
pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
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PDF描述 |
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| DS2154L | Enhanced E1 Single Chip Transceiver |
| DS2154LN | Enhanced E1 Single Chip Transceiver |
| DS2154 | WSD 151 SOLDERING STATION 230V UKWSD 151 SOLDERING STATION 230V UK; Frequency, supply max:60Hz; Frequency, supply min:50Hz; Height:101mm; Length:166mm; Power, input:150W; Temperature range:50(degree C) - 550(degree C); Voltage, |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151DK | 功能描述:KIT TRANSCEIVER T1 DESIGN DS2151 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2151K | 功能描述:IC TXRX T1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS2151Q | 制造商:DAL 功能描述:2151 DAL'95 NOTES 制造商:Maxim Integrated Products 功能描述:PCM TRANSCEIVER, Single, T-1(DS1), 44 Pin, Plastic, PLCC |
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
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