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參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 661K |
| 代理商： | CYW15G0201DXB |
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CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 8 of 46
RXSTA[2:0]
RXSTB[2:0]
LVTTL Output,
synchronous to the
selected RXCLKx
↑
output or
REFCLK
↑
[3]
input
Parallel Status Output
. These outputs change following the rising edge of the selected
receive interface clock.
When the Decoder is bypassed (DECMODE = LOW), RXSTx[1:0] become the two
low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the
presence of a Comma character in the Output Register. See
Table 16
for details.
When the Decoder is enabled (DECMODE = HIGH or MID), RXSTx[2:0] provide status of
the received signal. See
Table 18
,
Table 19
and
Table 20
for a list of Receive Character
status.
Receive Path Odd Parity
.
When parity generation is enabled (PARCTL
≠
LOW), the parity
output at these pins is valid for the data on the associated RXDx bus bits. When parity
generation is disabled (PARCTL = LOW) these output drivers are disabled (High-Z).
RXOPA
RXOPB
3-state, LVTTL
Output, synchronous
to the selected
RXCLKx
↑
output or
REFCLK
↑
[3]
input
Receive Path Clock and Clock Control
RXRATE
LVTTL Input
Static Control Input,
internal pull-down
Receive Clock Rate Select
. When LOW, the RXCLKx
±
recovered clock outputs are
complementary clocks operating at the recovered character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of
RXCLKx–. When HIGH, the RXCLKx
±
recovered clock outputs are complementary clocks
operating at half the character rate. Data for the associated receive channels should be
latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When REFCLK± is selected to clock the output registers (RXCKSELx = LOW), RXRATEx
is not interpreted. The RXCLKA± and RXCLKC± output clocks will follow the frequency and
duty cycle of REFCLK±.
Receive Character Clock Output or Clock Select Input
. When configured such that all
output data paths are clocked by the recovered clock (RXCKSEL = MID), these true and
complement clocks are the receive interface clocks which are used to control timing of
output data (RXDx[7:0], RXSTx[2:0] and RXOPx). These clocks are output continuously at
either the dual-character rate (1/20
th
the serial symbol-rate) or character rate (1/10
th
the
serial symbol-rate) of the data being received, as selected by RXRATE.
RXCLKA
±
RXCLKB
±
3-state, LVTTL
Output clock or
Static control input
When configured such that all output data paths are clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKA
±
and RXCLKC
+
output drivers present
a buffered and delayed form of REFCLK. RXCLKA
±
and RXCLKC
+
are buffered forms of
REFCLK that are slightly different in phase. This phase difference allows the user to select
the optimal setup/hold timing for their specific interface.
When RXCKSEL = HIGH and dual-channel bonding is enabled, one of the recovered clocks
from channels A or B is selected to present bonded data from channels A and B. RXCLKA
±
output the recovered clock from either receive channel A or receive channel B as selected
by RXCLKB+ to clock the bonded output data from channels A and B. See
Table 14
for
details.
When RXCKSEL = LOW and dual-channel bonding is enabled, REFCLK is selected to
present bonded data from channels A and B. RXCLKA
±
and RXCLKC
+
output drivers
present a buffered and delayed form of REFCLK. The master channel for bonding is
selected by RXCLKB+ (which acts as an input in this mode) to clock the bonded output data
from channels A and B. See
Table 14
for details.
Receive Clock Mode
. Selects the receive clock-source used to transfer data to the Output
Registers.
When LOW, both Output Registers are clocked by REFCLK. RXCLKB
±
outputs are disabled
(High-Z), and RXCLKA
±
and RXCLKC+ present buffered and delayed forms of REFCLK.
When MID, each RXCLKx
±
output follows the recovered clock for the respective channel,
as selected by RXRATE. When the 10B/8B Decoder and Elasticity Buffer are bypassed
(DECMODE = LOW), RXCKSEL must be MID.
RXCKSEL
3-Level Select
[4]
Static Control Input
When HIGH, and channel bonding is enabled in dual-channel mode (RX modes 2 and 3),
RXCLKA
±
outputs the recovered clock from either receive channel A or receive channel B
as selected by RXCLKB+. These output clocks may operate at the character-rate or half the
character-rate as selected by RXRATE.
Pin Descriptions
CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
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| CYW15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYW15G0201DXB-BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYW15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
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