參數(shù)資料
型號(hào): CYW15G0201DXB
廠商: Cypress Semiconductor Corp.
英文描述: Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器)
中文描述: 雙通道HOTLink II收發(fā)器(雙通道的HOTLink二收發(fā)器)
文件頁(yè)數(shù): 28/46頁(yè)
文件大?。?/td> 661K
代理商: CYW15G0201DXB
CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 28 of 46
JTAG Support
The CYP(V)(W)15G0201DXB contains a JTAG port to allow
system level diagnosis of device interconnect. Of the available
JTAG modes, only boundary scan is supported. This capability
is present only on the LVTTL inputs and outputs and the
REFCLK
±
clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
JTAG ID
The JTAG device ID for the CYP(V)(W)15G0201DXB is
‘1C80C069’x.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11, respectively.
Receive BIST
Detected LOW
Monitor Data
Received
RXSTx =
BIST_START (101)
No
RX PLL
Out of Lock
Yes, RXSTx =
BIST_DATA_COMPARE (000)/ BIST_COMMAND_COMPARE(001)
Compare
Next Character
Auto-Abort
Condition
Mismatch
End-of-BIST
State
Yes, RXSTx =
BIST_LAST_BAD (100)
Yes
No
No, RXSTx =
BIST_ERROR (110)
Data or
Command
Match
Command
RXSTx =
BIST_COMMAND_COMPARE (001)
End-of-BIST
State
Data
Yes, RXSTx =
BIST_LAST_GOOD (010)
No
RXSTx =
BIST_DATA_COMPARE (000)
Elasticity
Buffer Error
Start of
BIST Detected
RXSTx =
BIST_WAIT (111)
Yes
RXSTx =
BIST_START (101)
No
Figure 4. Receive BIST State Machine
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