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參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 661K |
| 代理商： | CYW15G0201DXB |
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CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 22 of 46
Transmit Channels
When OELE is HIGH, the signals on the BOE[3:0] inputs
directly control the power enables for the Serial Drivers. When
BOE[3:0] input is HIGH, the associated Serial Driver is
enabled. When BOE[3:0] input is LOW, the associated Serial
Driver is disabled and powered down. If both Serial Drivers of
a channel are disabled, the internal logic for that channel is
powered down. When OELE returns LOW, the value present
on the BOE[3:0] inputs are latched in the Output Enable Latch.
Device Reset State
When the CYP(V)(W)15G0201DXB is reset by the assertion
of TRSTZ, the Transmit Enable and Receive Enable Latches
are both cleared, and the BIST Enable Latch is preset. In this
state, all transmit and receive channels are disabled, and BIST
is disabled on all channels.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the BOE[3:0]
inputs while the OELE and RXLE signals are raised and
lowered. For systems that do not require dynamic control of
power, or want the device to power up in a fixed configuration,
it is also possible to strap the RXLE and OELE control signals
HIGH to permanently enable their associated latches.
Connection of the associated BOE[3:0] signals HIGH will then
enable the respective transmit and receive channels as soon
as the TRSTZ signal is deasserted.
Output Bus
Each receive channel presents a 12-signal output bus
consisting of
an 8-bit data bus
a 3-bit status bus
a parity bit.
The signals present on this output bus are modified by the
present operating mode of the CYP(V)(W)15G0201DXB as
selected by DECMODE. The bits are assigned per
Table 15
.
Table 15. Output Register Bit Assignments
[16]
When the 10B/8B Decoder is bypassed (DECMODE = LOW),
the framed 10-bit and a single status bit are presented at the
receiver Output Register. The status output indicates if the
character in the Output Register is one of the selected framing
characters. The bit usage and mapping of the external signals
to the raw 10B transmission character is shown in
Table 16
.
Table 16. Decoder Bypass Mode (DECMODE = LOW)
The COMDETx status outputs operate the same regardless of
the bit combination selected for character framing by the
FRAMCHAR input. They are HIGH when the character in the
Output Register contains the selected framing character at the
proper character boundary, and LOW for all other bit combina-
tions.
When the low-latency framer and half-rate receive port
clocking are also enabled (RFMODE = LOW, RXRATE =
HIGH, and RXCKSEL
≠
LOW), the framer will stretch the
recovered clock to the nearest 20-bit boundary such that the
rising edge of RXCLKx+ occurs when COMDETx is present on
the associated output bus.
When the Cypress or Alternate Mode Framer is enabled and
half-rate receive port clocking is also enabled (RFMODE
≠
LOW and RXRATE = HIGH), the output clock is not modified
when framing is detected, but a single pipeline stage may be
added or subtracted from the data stream by the framer logic
such that the rising edge of RXCLKx+ occurs when COMDETx
is present on the associated output bus.
This adjustment only occurs when the framer is enabled
(RFEN = HIGH). When the framer is disabled, the clock
boundaries are not adjusted, and COMDETx may be asserted
during the rising edge of RXCLKx– (if an odd number of
characters were received following the initial framing).
Parity Generation
In addition to the eleven data and status bits that are presented
by each channel, an RXOPx parity output is also available on
each channel. This allows the CYP(V)(W)15G0201DXB to
support ODD parity generation for each channel. To handle a
wide
range
of
system
CYP(V)(W)15G0201DXB supports multiple different forms of
parity generation including no parity. When the Decoders are
enabled (DECMODE
≠
LOW), parity can be generated on
the RXDx[7:0] character
the RXDx[7:0] character and RXSTx[2:0] status.
When the Decoders are bypassed (DECMODE = LOW), parity
can be generated on
the RXDx[7:0] and RXSTx[1:0] bits
the RXDx[7:0] and RXSTx[2:0] bits.
environments,
the
Note:
16. The RXOPx outputs are also driven from the associated Output Register, but their interpretation is under the separate control of PARCTL.
Signal Name
RXSTx[2]
(LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
(MSB)
DECMODE = LOW
COMDETx
DOUTx[0]
DOUTx[1]
DOUTx[2]
DOUTx[3]
DOUTx[4]
DOUTx[5]
DOUTx[6]
DOUTx[7]
DOUTx[8]
DOUTx[9]
DECMODE = MID
or HIGH
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
Signal Name
RXSTx[2]
(LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
(MSB)
Bus Weight
COMDETx
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10B Name
a
b
c
d
e
i
f
g
h
j
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| CYW15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYW15G0201DXB-BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
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