參數(shù)資料
型號： CYW15G0201DXB
廠商： Cypress Semiconductor Corp.
英文描述： Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器)
中文描述： 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器）
文件頁數(shù)： 31/46頁
文件大?。?/td> 661K
代理商： CYW15G0201DXB
CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 31 of 46
CYP(V)(W)15G0201DXB AC Characteristics
Over the Operating Range
Parameter
Transmitter LVTTL Switching Characteristics
f
TS
TXCLKx Clock Frequency
t
TXCLK
TXCLKx Period
t
TXCLKH [30]
TXCLKx HIGH Time
t
TXCLKL [30]
TXCLKx LOW Time
t
TXCLKR [30, 31, 32]
TXCLKx Rise Time
t
TXCLKF [30, 31, 32]
TXCLKx Fall Time
t
TXDS
Transmit Data Set-Up Time to
TXCLKx
↑
(TXCKSEL
≠
LOW)
t
TXDH
Transmit Data Hold Time from TXCLKx
↑
(TXCKSEL
≠
LOW)
f
TOS
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
t
TXCLKO
TXCLKO Period
t
TXCLKOD+
TXCLKO+ Duty Cycle with 60% HIGH time
t
TXCLKOD–
TXCLKO– Duty Cycle with 40% HIGH time
Receiver LVTTL Switching Characteristics
f
RS
RXCLKx Clock Output Frequency
t
RXCLKP
RXCLKx Period
t
RXCLKH
RXCLKx HIGH Time (RXRATE = LOW)
RXCLKx HIGH Time (RXRATE = HIGH)
t
RXCLKL
RXCLKx LOW Time (RXRATE = LOW)
RXCLKx LOW Time (RXRATE = HIGH)
t
RXCLKD
RXCLKx Duty Cycle centered at 50%
t
RXCLKR[30]
RXCLKx Rise Time
t
RXCLKF[30]
RXCLKx Fall Time
t
RXDV–[33]
Status and Data Valid Time to RXCLKx (RXCKSEL = HIGH or MID)
Status and Data Valid Time to RXCLKx
(Half Rate Recovered Clock)
t
RXDV+[33]
Status and Data Valid Time From RXCLKx
(RXCKSEL = HIGH or MID)
Status and Data Valid Time From RXCLKx
(Half Rate Recovered Clock)
REFCLK Switching Characteristics
Over the Operating Range
f
REF
REFCLK Clock Frequency
t
REFCLK
REFCLK Period
t
REFH
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
t
REFL
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
t
REFD[34]
REFCLK Duty Cycle
t
REFR[30, 31, 32]
REFCLK Rise Time (20% – 80%)
t
REFF[30, 31, 32]
REFCLK Fall Time (20% – 80%)
t
TREFDS
Transmit Data Set-up Time to
REFCLK (TXCKSEL
=
LOW)
t
TREFDH
Transmit Data Hold Time from REFCLK
(TXCKSEL
=
LOW)
Notes:
28. This parameter is 154 MHz for CYW15G0201DXB.
29. This parameter is 6.49 ns for CYW15G0201DXB.
30. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
31. The ratio of rise time to falling time must not vary by greater than 2:1.
32. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
33. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
34. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30%–70%.
Description
Min.
Max.
Unit
19.5
6.66
[29]
2.2
2.2
0.2
0.2
1.7
0.8
19.5
6.66
[29]
–1.0
–0.5
150
[28]
51.28
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
1.7
1.7
150
[28]
51.28
+0.5
+1.0
9.75
6.66
[29]
2.33
[30]
5.66
2.33
[30]
5.66
–1.0
0.3
0.3
5UI – 1.5
5UI – 1.0
5UI – 1.8
5UI – 2.3
150
[28]
102.56
26.64
52.28
26.64
52.28
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19.5
6.66
[29]
5.9
2.9
[30]
5.9
2.9
[30]
30
150
[28]
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
70
2
2
1.7
0.8
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