參數(shù)資料
型號(hào): CYW15G0201DXB
廠商: Cypress Semiconductor Corp.
英文描述: Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器)
中文描述: 雙通道HOTLink II收發(fā)器(雙通道的HOTLink二收發(fā)器)
文件頁(yè)數(shù): 29/46頁(yè)
文件大小: 661K
代理商: CYW15G0201DXB
CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 29 of 46
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State.......................................–0.5V to V
CC
+ 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V
CC
+ 0.5V
CYP(V)(W)15G0201DXB DC Electrical Characteristics
Over the Operating Range
Static Discharge Voltage..........................................> 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Power-up requirements
: The CYP(V)(W)15G0201DXB
requires one power-supply. The voltage on any input or I/O pin
cannot exceed the power pin during power-up.
Operating Range
Range
Ambient Temp.
0°C to +70°C
–40°C to +85°C
V
CC
Commercial
Industrial
+3.3V ±5%
+3.3V ±5%
Parameter
LVTTL-compatible Outputs
V
OHT
Output HIGH Voltage
V
OLT
Output LOW Voltage
I
OST
Output Short Circuit Current
I
OZL
High-Z Output Leakage Current
LVTTL-compatible Inputs
V
IHT
Input HIGH Voltage
V
ILT
Input LOW Voltage
I
IHT
Input HIGH Current
Description
Test Conditions
Min.
Max.
Unit
I
OH
=
4 mA, V
CC
= Min.
I
OL
= 4 mA, V
CC
= Min.
V
OUT
= 0V
[19]
2.4
0
–20
–20
V
CC
0.4
–100
20
V
V
mA
μA
2.0
–0.5
V
CC
+ 0.3
0.8
1.5
+40
–1.5
–40
+200
–200
V
V
REFCLK Input, V
IN
= V
CC
Other Inputs, V
IN
= V
CC
REFCLK Input, V
IN
= 0.0V
Other Inputs, V
IN
= 0.0V
V
IN
= V
CC
V
IN
= 0.0V
mA
μA
mA
μA
μA
μA
I
ILT
Input LOW Current
I
IHPDT
I
ILPUT
LVDIFF Inputs: REFCLK±
V
DIFF[20]
Input Differential Voltage
V
IHHP
Highest Input HIGH Voltage
V
ILLP
Lowest Input LOW voltage
V
COM[21]
Common Mode Range
3-Level Inputs
V
IHH
3-Level Input HIGH Voltage
V
IMM
3-Level Input MID Voltage
V
ILL
3-Level Input LOW Voltage
I
IHH
Input HIGH Current
I
IMM
Input MID current
I
ILL
Input LOW current
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±
V
OHC
Output HIGH Voltage
(V
CC
referenced)
Input HIGH current with internal pull-down
Input LOW current with internal pull-up
400
1.0
0.0
1.0
V
CC
V
CC
V
CC
/2
V
CC
– 1.2V
mV
V
V
V
Min.
V
CC
Max.
Min.
V
CC
Max.
Min.
V
CC
Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
0.87 * V
CC
0.47 * V
CC
0.53 * V
CC
0.0
V
CC
V
V
V
μA
μA
μA
0.13 * V
CC
200
50
–200
–50
100
differential load
150
differential load
V
CC
– 0.5
V
CC
– 0.5
V
CC
– 0.2
V
CC
– 0.2
V
V
Notes:
19. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
20. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when
the true (+) input is more positive than the complement (
) input. A logic-0 exists when the complement (
) input is more positive than true (+) input.
21. The common mode range defines the allowable range of REFCLK+ and REFCLK
when REFCLK+ = REFCLK
. This marks the zero-crossing between the
true and complement inputs as the signal switches between a logic-1 and a logic-0.
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