參數(shù)資料
型號(hào)： CYW15G0201DXB
廠商： Cypress Semiconductor Corp.
英文描述： Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器)
中文描述： 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器）
文件頁(yè)數(shù)： 32/46頁(yè)
文件大?。?/td> 661K
代理商： CYW15G0201DXB
CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 32 of 46
t
RREFDA[35]
t
RREFDV
t
REFADV–
t
REFADV+
t
REFCDV–
t
REFCDV+
t
REFRX
[30, 32]
Transmit Serial Outputs and TX PLL Characteristics
t
B
Bit Time
t
RISE[30]
CML Output Rise Time 20% – 80% (CML Test Load)
Receive Data Access Time from REFCLK (RXCKSEL
=
LOW)
Receive Data Valid Time from REFCLK
(RXCKSEL
=
LOW)
Received Data Valid Time to RXCLKA (RXCKSEL = LOW)
Received Data Valid Time from RXCLKA (RXCKSEL = LOW)
Received Data Valid Time to RXCLKC (RXCKSEL = LOW)
Received Data Valid Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Extracted Received Clock Frequency
9.5
ns
ns
ns
ns
ns
ns
%
2.5
10UI – 4.7
0.5
10UI – 4.3
–0.2
–0.02
+0.02
5100
60
100
180
60
100
180
666
[36]
270
500
1000
270
500
1000
25
11
200
ps
ps
ps
ps
ps
ps
ps
ps
ps
us
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
IEEE 802.3z
IEEE 802.3z
t
FALL[30]
CML Output Fall Time 80% – 20% (CML Test Load)
t
DJ[30, 37, 39]
t
RJ[30, 38, 39]
t
TXLOCK
Receive Serial Inputs and CDR PLL Characteristics
t
RXLOCK
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
t
RXUNLOCK
Receive PLL Unlock Rate
t
JTOL[39]
Total Jitter Tolerance
t
DJTOL[39]
Deterministic Jitter Tolerance
Capacitance
[30]
Parameter
C
INTTL
TTL Input Capacitance
C
INPECL
PECL input Capacitance
Notes:
35. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
and set-up
time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW)
could be used to clock the receive data out of the device.
36. This parameter is 649 ps for CYW15G0201DXB.
37. While sending continuous K28.5s, outputs loaded to a balanced 100
load, measured at the cross point of the differential outputs over the operating range.
38. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range.
39. Total jitter is calculated at an assumed BER of 1E
12. Hence: Total Jitter (t
)
=
(t
* 14) + t
.
40. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259M, SMPTE 292M, OBSAI RP3, CPRI, ESCON, FICON, Fibre
Channel and DVB-ASI.
41. Receiver UI (Unit Interval) is calculated as 1/(f
REF
*20) (when RXRATE
=
HIGH) or 1/(f
REF
* 10) (when RXRATE
=
LOW) if no data is being received, or 1/(f
REF
* 20)
(when RXRATE
=
HIGH) or 1/(f
REF
* 10) (when RXRATE
=
LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
B.
Deterministic Jitter (peak-peak)
Random Jitter (
σ
)
Transmit PLL lock to REFCLK
376K
376K
46
UI
[41]
UI
UI
ps
ps
IEEE 802.3z
[40]
IEEE 802.3z
[40]
600
370
Description
Test Conditions
Max.
7
4
Unit
pF
pF
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V
CYP(V)(W)15G0201DXB AC Characteristics
Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
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