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參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 46/46頁 |
| 文件大小： | 661K |
| 代理商： | CYW15G0201DXB |
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CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 46 of 46
Document History Page
Document Title: CYP(V)(W)15G0201DXB Dual-channel HOTLink II Transceiver
Document Number: 38-02058
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
**
116633
07/16/02
SDR
New Data Sheet
*A
119705
10/30/02
LNM
Revised receive block diagram for RXCLKC+ signal
Changed TXPERx description
Changed TXCLKO description
Corrected RXCLKB- description in REFCLK clocking mode to be disabled
Removed reference to ATM support
Removed the LOW setting for FRAMCHAR and related references
Changed the I
OST
boundary values
Changed V
ODIF
and V
OLC
for CML output
Changed the t
TXCLKR
and t
TXCLKF
min. values
Changed t
TXDS
and t
TXDH
and t
TREFDS
and t
TREFDH
Changed t
REFADV–
, t
REFCDV–
, and t
REFCDV+
Changed the JTAG ID from 0C80C069 to 1C80C069
Added a section for characterization and Standards compliance
Changed I/O type of RXCLKC in I/O coordinates table
*B
122212
12/28/02
RBI
Document Control minor change
*C
122547
12/9/2002
CGX
Changed Minimum t
RISE
/t
FALL
for CML
Changed t
RXLOCK
Changed t
DJ, tRJ
Changed t
JTOL
Changed t
TXLOCK
Changed t
RXCLKH
, t
RXCLKL
Changed t
TXCLKOD+
, t
TXCLKOD-
Changed Power specs
Changed verbiage...Paragraph: Clock/Data Recovery
Changed verbiage...Paragraph: Range Control
Added Power-up Requirements
*D
124548
02/13/03
LJN
Minor Change: Corrected errors and Power-up notes
*E
124995
04/15/03
POT
Changed CYP15G0201DXB to CYP(V)15G0201DXB type corresponding
to the Video-compliant parts
Reduced the lower limit of the serial signaling rate from 200 Mbaud to
195 Mbaud and changed the associated specifications accordingly
*F
128368
07/28/03
PDS
Revised the value of t
RREFDV,
t
REFADV+ and
t
REFCDV+
When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made
appropriate changes to reflect this invalid condition.
Removed requirement of AC coupling for Serial I/Os for interfacing with
LVPECL I/Os.
Changed LFIx to Asynchronous output.
Expanded the CDR Range Controller’s permissible frequency offset
between incoming serial signalling rate and Reference clock from
±200-PPM to ±1500-PPM (changed parameter t
REFRX
).
Added Table for RXSTx[2:0] status for non-bonded (Independent Channel)
mode of operation for clarity. Separated the Receive BIST status to a new
Table for clarity.
*G
131900
01/30/04
PDS
*H
338721
See ECN
SUA
Added CYW15G0201DXB part number for OBSAI RP3 compliance to
support operating data rate up to 1540 MBaud. Made changes to reflect
OBSAI RP3 and CPR compliance. Added Pb-Free Package option for all
parts listed in the datasheet.
Changed MBd to MBaud in SPDSEL pin description
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYW15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0201DXB-BBI | 功能描述:電信線路管理 IC Dual Ch XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0201DXB-BBXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYW15G0201DXB-BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYW15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
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