參數(shù)資料
型號: CYW2336
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 諧振器
英文描述: Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers(帶2.0-GHz 預(yù)標定器的串聯(lián)輸入PLL)
中文描述: DUAL PRESCALER, PDSO20
封裝: 0.173 INCH, MO-153, TSSOP-20
文件頁數(shù): 1/10頁
文件大?。?/td> 157K
代理商: CYW2336
Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers
CYW2336
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 14, 2000, rev. **
Features
Operating voltage 2.7V to 5.5V
Operating frequency to 2.0 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
Lock detect feature
Power-down mode I
CC
< 1 μA typical at 3.0V
Serial data input accepts data clock rates as low as
1 kHz
Low power/voltage operation with low current standby
mode
On-chip reference oscillator
Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
Applications
The Cypress CYW2336 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The CYW2336 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.0-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 33 mW.
Dual PLL Block Diagram
Pin Configuration
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
1
2
3
4
5
6
7
8
9
10
Binary 7-Bit
Swallow Counter
Prescaler
64/65 or
128/129
Phase
Detector
Latch
PPLL1
Binary 11-Bit
Programmable Counter
20-Bit Latch
20-Bit Latch
Prescaler
64/65 or
128/129
Cntrl 22-Bit
Shift
Reg.
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Latch
PPLL2
Refer15-Bit
Refer15-Bit
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Selector
Charge
Pump
Power
Control
GND
VP2
GND
GND
GND
V
CC
V
CC
F
IN
1
(6)
F
IN
1#
OSC_IN
LE
DATA
CLOCK
F
2
(15)
F
IN
2#
VP1
D
O
PLL1
F
O
/LD
D
O
PLL2
Latch
Selector
fp1
fr1
fr2
fp2
(4)
(7)
(1)
(20)
(2)
(3)
(18)
(10)
(19)
(17)
(14)
(5)
(8)
(13)
(11)
(16)
(12)
OSC_OUT
(9)
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