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參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 661K |
| 代理商： | CYW15G0201DXB |
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CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 20 of 46
In all settings where the Decoder is enabled, the receive paths
may be operated as separate channels or bonded to form
dual-channel buses.
Receive BIST Operation
The Receiver interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x]
signals listed in
Table 9
(when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated receive
channel becomes a signature pattern generator and checker
by logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence that
includes all Data and Special Character codes, including the
explicit violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Transmitter(s). If the receive channels
are configured for common clock operation (RXCKSEL
≠
MID)
each pass is preceded by a 16-character Word Sync
Sequence. When synchronized with the received data stream,
the associated Receiver checks each character in the
Decoder with each character generate by the LFSR and
indicates compare errors and BIST status at the RXSTx[2:0]
bits of the Output Register. See
Table 20
for details.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator/checker in the associated
Receive channel (or the BIST generator in the associated
Transmit channel). When BISTLE returns LOW, the values of
all BOE[x] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned HIGH. All captured signals in the BIST Enable Latch
are set HIGH (i.e., BIST is disabled) following a device reset
(TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0 This code D0.0 is sent only once per BIST loop. The
status of the BIST progress and any character mismatches is
presented on the RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
are presented when the Decoder is bypassed and BIST is
enabled on a receive channel.
The specific status reported by the BIST state machine are
listed in
Table 18
. These same codes are reported on the
receive status outputs regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note entitled “HOTLink
Built-In Self-Test.” The sequence compared by the
CYP(V)(W)15G0201DXB when RXCKSEL = MID is identical
to that in the CY7B933 and CY7C924DX, allowing interop-
erable systems to be built when used at compatible serial
signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for common clock
operation (RXCKSEL
≠
MID) each pass must be preceded by
a 16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations.
This is automatically generated by the transmitter when its
local RXCKSEL
≠
MID and Encoder is enabled.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low Latency
framer is enabled (RFMODE = LOW), the framer will misalign
to an aliased SYNC character within the BIST sequence. If the
Alternate Multi-Byte Framer is enabled (RFMODE = HIGH)
and the Receiver outputs are clocked relative to a recovered
clock, it is generally necessary to frame the receiver before
BIST is enabled. If the receive outputs are clocked relative to
REFCLK (RXCKSEL = LOW), the transmitter precedes every
511 character BIST sequence with a 16-character Word Sync
Sequence.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using an Elasticity Buffer read-clock that
is asynchronous in both frequency and phase from the
Elasticity Buffer write clock, or to use a read clock that is
frequency coherent but with uncontrolled phase relative to the
Elasticity Buffer write clock.
Each Elasticity Buffer is a minimum of 10 characters deep, and
supports a 12-bit-wide data path. It is capable of supporting a
decoded character, three status bits, and a parity bit for each
character present in the buffer. The write clock for these
buffers is always the recovered clock for the associated read
channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
character-rate REFCLK
recovered clock from the same receive channel
recovered clock from an alternate receive channel
These Elasticity Buffers are also used to align the output data
streams when both channels are bonded together. More
details on how the Elasticity Buffer is used for Independent
Channel Modes and Channel Bonded Modes is discussed in
the next section. The Elasticity Buffers are bypassed
whenever the Decoders are bypassed (DECMODE = LOW).
When the Decoders and Elasticity Buffers are bypassed,
RXCKSELx must be set to MID.
Receive Modes
The operating mode of the receive path is set through the
RXMODE[1:0] inputs. The ‘Reserved for test’ settings
(RXMODE0=M) is not allowed, even if the receiver is not being
used. A[1:0] settings are ignored as long as they are not test
modes. It will stop normal function of the device. When the
decoder is disabled, the RX MODE. These modes determine
the type (if any) of channel bonding and status reporting. The
different receive modes are listed in
Table 13
. When
RXMODE[1] = MID or RXMODE[0] = MID the resulting modes
are reserved for test.
Independent Channel Modes
In independent channel modes (RX Modes 0 and 1, where
RXMODE[1] = LOW), both receive paths may be clocked in
any clock mode selected by RXCKSEL.
When RXCKSEL = LOW, both channels are clocked by
REFCLK. RXCLKB± output is disabled (High-Z), and the
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