- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYW15G0201DXB (Cypress Semiconductor Corp.) Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 12/46頁 |
| 文件大小： | 661K |
| 代理商： | CYW15G0201DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 12 of 46
CYP(V)(W)15G0201DXB HOTLink II Operation
The CYP(V)(W)15G0201DXB is a highly configurable device
designed to support reliable transfer of large quantities of data,
using high-speed serial links, from one or multiple sources to
one or multiple destinations. This device supports two
single-byte or single-character channels that may be
combined to support transfer of wider buses.
CYP(V)(W)15G0201DXB Transmit Data Path
Operating Modes
The transmit path of the CYP(V)(W)15G0201DXB supports
two character-wide data paths. These data paths are used in
multiple operating modes as controlled by the TXMODE[1:0]
inputs.
Input Register
The bits in the Input Register for each channel support
different assignments, based on if the character is unencoded,
encoded with two control bits, or encoded with three control
bits. These assignments are shown in
Table 1
.
Each Input Register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the Encoder
is bypassed, the TXCTx[1:0] control bits are part of the
pre-encoded 10-bit character.
When the Encoder is enabled (TXMODE[1]
≠
LOW), the
TXCTx[1:0] bits are interpreted along with the associated
TXDx[7:0] character to generate the specific 10-bit trans-
mission character. When TXMODE[0]
≠
HIGH, an additional
special character select (SCSEL) input is also captured and
interpreted. This SCSEL input is used to modify the encoding
of the associated characters. When the transmit Input
Registers are clocked by a common clock (TXCLKA
↑
or
REFCLK
↑
), this SCSEL input can be changed on a
clock-by-clock basis and affects both channels.
When operated with a separate input clock on each transmit
channel, this SCSEL input is sampled synchronous to
TXCLKA
↑
. While the value on SCSEL still affects both
channels, it is interpreted when the character containing it is
read from the transmit Phase-Align Buffer (where both paths
are internally clocked synchronously).
Phase-Align Buffer
Data from the Input Registers is passed either to the Encoder
or to the associated Phase-Align Buffer. When the transmit
paths are operated synchronous to REFCLK
↑
(TXCKSEL =
LOW and TXRATE = LOW), the Phase-Align Buffers are
bypassed and data is passed directly to the parity check and
Encoder blocks to reduce latency.
When an Input-Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL
≠
LOW) or if
data
is
captured
on
both
(TXRATE = HIGH), the Phase-Align Buffers are enabled.
These buffers are used to absorb clock phase differences
between the presently selected input clock and the internal
character clock.
Initialization of these Phase-Align buffers takes place when the
TXRST input is sampled by two consecutive rising edges of
REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK
↑
is set. TXRST is an
asynchronous input, but is sampled internally to synchronize
it to the internal transmit path state machines.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK
↑
;
i.e.,
±
180°. This time shift allows the delay paths of the
character clocks (relative to REFLCK
↑
) to change due to
operating voltage and temperature, while not affecting the
design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK
↑
, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the
associated TXPERx output. This output indicates a continuous
error until the Phase-Align Buffer is reset. While the error
remains active, the transmitter for the associated channel
outputs a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes, it is also possible to reset the
Phase-Align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is
configured for generation of atomic Word Sync Sequences
(TXMODE[1] = MID) and a Phase-Align Buffer error is
present, the transmission of a Word Sync Sequence will
recenter the Phase Align Buffer and clear the error condition.
[6]
edges
of
REFCLK
Notes:
5.
6.
The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.
One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a
complete 16-character Word Sync Sequence for proper receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word
Sync Sequence to ensure proper operation.
Table 1. Input Register Bit Assignments
[5]
Signal Name
TXDx[0]
(LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
(MSB)
SCSEL
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
N/A
Encoded
2-bit
Control
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
N/A
3-bit
Control
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
SCSEL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYW15G0401DXB | Quad HOTLink II Transceiver(四熱連接II收發(fā)器) |
| CYW2330 | Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers |
| CYW2331 | Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers |
| CYW2336 | Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers(帶2.0-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
| CYW256OXC | Multiconductor Paired Security UTP Cable; Number of Conductors:8; Conductor Size AWG:23; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:4; Impedance:100ohm; Jacket Color:Gray RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0201DXB-BBI | 功能描述:電信線路管理 IC Dual Ch XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0201DXB-BBXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYW15G0201DXB-BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYW15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。