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參數(shù)資料
| 型號： | CYW15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| 中文描述： | 雙通道HOTLink II收發(fā)器（雙通道的HOTLink二收發(fā)器） |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 661K |
| 代理商： | CYW15G0201DXB |
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CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 11 of 46
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable
.
Active HIGH. When OELE = HIGH, the signals
on the BOE[3:0] inputs directly control the OUTxy
±
differential drivers. When the BOE[x]
input is HIGH, the associated OUTxy
±
differential driver is enabled. When the BOE[x] input
is LOW, the associated OUTxy
±
differential driver is powered down. When OELE returns
LOW, the last values present on BOE[3:0] are captured in the internal Output Enable Latch.
The specific mapping of BOE[3:0] signals to transmit output enables is listed in
Table 9
.
If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs.
Receive Channel Power-Control Latch Enable
. Active HIGH. When RXLE = HIGH, the
signals on the BOE[3:0] inputs directly control the power enables for the receive PLLs and
analog logic. When the BOE[3:0] input is HIGH, the associated receive channel A and
receive channel B PLL and analog logic are active. When the BOE[3:0] input is LOW, the
associated receive channel A and receive channel B PLL and analog logic are placed in a
non-functional power saving mode. When RXLE returns LOW, the last values present on
BOE[3:0] are captured in the internal RX PLL Enable Latch. The specific mapping of
BOE[3:0] signals to the associated receive channel enables is listed in
Table 9
. When the
device is reset (TRSTZ is sampled LOW), the latch is reset to disable both receive channels.
Transmit and Receive BIST Latch Enable
. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[3:0] inputs directly control the transmit and receive BIST enables. When
the BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated
transmit or receive channel is configured for normal data transmission or reception. When
BISTLE returns LOW, the last values present on BOE[3:0] are captured in the internal BIST
Enable Latch. The specific mapping of BOE[3:0] signals to transmit and receive BIST
enables is listed in
Table 9
. When the latch is closed, if the device is reset (TRSTZ is sampled
LOW), the latch is reset to disable BIST on all transmit and receive channels.
BIST, Serial Output, and Receive Channel Enables
. These inputs are passed to and
through the Output Enable Latch when OELE = HIGH, and captured in this latch when
OELE returns LOW. These inputs are passed to and through the BIST Enable Latch when
BISTLE = HIGH, and captured in this latch when BISTLE returns LOW. These inputs are
passed to and through the Receive Channel Enable Latch when RXLE = HIGH, and
captured in this latch when RXLE returns LOW.
Link Fault Indication Output
. Active LOW. LFIx is the logical OR of four internal conditions:
RXLE
LVTTL Input,
asynchronous,
internal pull-up
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[3:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LVTTL Output,
Asynchronous
1. Received serial data frequency outside expected range.
2. Analog amplitude below expected levels.
3. Transition density lower than expected.
4. Receive Channel disabled.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained HIGH for
>5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automat-
ically upon application of power to the device.
JTAG Test Clock
.
TCLK
LVTTL Input,
internal pull-down
3-State
LVTTL Output
LVTTL Input,
internal pull-up
TDO
Test Data Out
. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
Power
V
CC
GND
+3.3V power.
Signal and Power Ground for all internal circuits.
Pin Descriptions
CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
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| CYW15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYW15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
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