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參數(shù)資料
| 型號： | CYRF69213 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 65/85頁 |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213 |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 65 of 85
Mnemonic
IO_CFG_ADR
Address
1
0x0D
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
IRQ OD
IRQ POL
MISO OD
XOUT OD
PACTL OD
PACTL GPIO
SPI 3PIN
IRQ GPIO
To use a GPIO pin as an input, the output mode must be set to open drain, and a ‘1’ written to the corresponding output register bit.
Bit 7
IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin
as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
IO
pin voltage.
Bit 6
IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal
polarity to be active LOW.
Bit 5
MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the
MISO pin as a standard CMOS output, with the output ‘1’ drive voltage being equal to the V
IO
pin voltage.
Bit 4
XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the
XOUT pin as a standard CMOS output, with the output ’1’ drive voltage being equal to the V
IO
pin voltage.
Bit 3
PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the
PACTL pin as a standard CMOS output, with the output ’1’ drive voltage being equal to the V
IO
pin voltage.
Bit 2
PACTL Pin Function. When this bit is set the PACTL pin is available for use as a GPIO.
Bit 1
SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI
interface operates in ‘3-Wire Mode’ combining MISO and MOSI on the same pin (SDAT), and the MISO pin is available as a
GPIO pin.
Bit 0
IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is con-
figurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed
onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
Mnemonic
GPIO_CTRL_ADR
Address
0x0E
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
-
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
Function
XOUT OP
MISO OP
PACTL OP
IRQ OP
XOUT IP
MISO IP
PACTL IP
IRQ IP
To use a GPIO pin as an input, the output mode must be set to open drain, and a ’1’ written to the corresponding output register bit.
Bit 7
XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin.
Bit 6
MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin.
Bit 5
PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin.
Bit 4
IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin.
Bit 3
XOUT Input. When the XOUT pin is configured to be a GPIO, the state of this bit reflects the voltage on the XOUT pin.
Bit 2
MISO Input. When the MISO pin is configured to be a GPIO, the state of this bit reflects the voltage on the MISO pin.
Bit 1
PACTL Input. When the PACTL pin is configured to be a GPIO, the state of this bit reflects the voltage on the PACTL pin.
Bit 0
IRQ Input. When the IRQ pin is configured to be a GPIO, the state of this bit reflects the voltage on the IRQ pin.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | 功能描述:射頻接收器 PRoC LP COM RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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